soc/amd/picasso: add UPD for RV2 USB3 phy setting adjust

add UPD for RV2 USB3 phy setting adjust.

Note: it only for RV2 silicon and not available for RV/PCO.

Usb 3.1 PHY Parameters:
1. RX_EQ_DELTA_IQ_OVRD_VAL
	-Override value for rx_eq_delta_iq. Range 0-0xF
2. RX_EQ_DELTA_IQ_OVRD_EN
	-Enable override value for rx_eq_delta_iq. Range 0-0x1
3. Override value for rx_vref_ctrl. Range 0 - 0x1F
4. Enable override value for rx_vref_ctrl. Range 0 - 0x1
5. Override value for tx_vboost_lvl: 0 - 0x7.
6. Enable override value for tx_vboost_lvl. Range: 0 - 0x1
7. Override value for rx_vref_ctrl. Range 0 - 0x1F
8. Enable override value for rx_vref_ctrl. Range 0 - 0x1
9. Override value for tx_vboost_lvl: 0 - 0x7.
10. Enable override value for tx_vboost_lvl. Range: 0 - 0x1

BUG=b:175192931
TEST=Build/verify the valule will been apply on dirinboz

Change-Id: I1d5f69e840952cc5171af1ce8597628d1bede5cb
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50240
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2 files changed, 82 insertions, 0 deletions

diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
index e014ce302c..9b0dd9a855 100644
--- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
+++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
@@ -134,6 +134,47 @@ chip soc/amd/picasso
 		.tx_res_tune = 0x01,
 	}"
 
+	# Start RV2 USB3 PHY Parameters
+	register "usb3_phy_override" = "0"
+
+	# USB3 Port0 Default
+	register "usb3_phy_tune_params[0]" = "{
+			.rx_eq_delta_iq_ovrd_val = 0x0,
+			.rx_eq_delta_iq_ovrd_en = 0x0,
+	}"
+
+	# USB3 Port1 Default
+	register "usb3_phy_tune_params[1]" = "{
+			.rx_eq_delta_iq_ovrd_val = 0x0,
+			.rx_eq_delta_iq_ovrd_en = 0x0,
+	}"
+
+	# USB3 Port2 Default
+	register "usb3_phy_tune_params[2]" = "{
+			.rx_eq_delta_iq_ovrd_val = 0x0,
+			.rx_eq_delta_iq_ovrd_en = 0x0,
+	}"
+
+	# USB3 Port3 Default
+	register "usb3_phy_tune_params[3]" = "{
+			.rx_eq_delta_iq_ovrd_val = 0x0,
+			.rx_eq_delta_iq_ovrd_en = 0x0,
+	}"
+
+	# SUP_DIG_LVL_OVRD_IN Default
+	register "usb3_rx_vref_ctrl" = "0x10"
+	register "usb3_rx_vref_ctrl_en" = "0x00"
+	register "usb_3_tx_vboost_lvl" = "0x07"
+	register "usb_3_tx_vboost_lvl_en" = "0x00"
+
+	# SUPX_DIG_LVL_OVRD_IN Default
+	register "usb_3_rx_vref_ctrl_x" = "0x10"
+	register "usb_3_rx_vref_ctrl_en_x" = "0x00"
+	register "usb_3_tx_vboost_lvl_x" = "0x07"
+	register "usb_3_tx_vboost_lvl_en_x" = "0x00"
+
+	# End RV2 USB3 phy setting
+
 	# USB OC pin mapping
 	register "usb_port_overcurrent_pin[0]" = "USB_OC_PIN_0"	# USB C0
 	register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_1"	# USB C1
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
index 5ec9010680..a3c4573ce5 100644
--- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
+++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
@@ -134,6 +134,47 @@ chip soc/amd/picasso
 		.tx_res_tune = 0x01,
 	}"
 
+	# Start RV2 USB3 PHY Parameters
+	register "usb3_phy_override" = "0"
+
+	# USB3 Port0 Default
+	register "usb3_phy_tune_params[0]" = "{
+			.rx_eq_delta_iq_ovrd_val = 0x0,
+			.rx_eq_delta_iq_ovrd_en = 0x0,
+	}"
+
+	# USB3 Port1 Default
+	register "usb3_phy_tune_params[1]" = "{
+			.rx_eq_delta_iq_ovrd_val = 0x0,
+			.rx_eq_delta_iq_ovrd_en = 0x0,
+	}"
+
+	# USB3 Port2 Default
+	register "usb3_phy_tune_params[2]" = "{
+			.rx_eq_delta_iq_ovrd_val = 0x0,
+			.rx_eq_delta_iq_ovrd_en = 0x0,
+	}"
+
+	# USB3 Port3 Default
+	register "usb3_phy_tune_params[3]" = "{
+			.rx_eq_delta_iq_ovrd_val = 0x0,
+			.rx_eq_delta_iq_ovrd_en = 0x0,
+	}"
+
+	# SUP_DIG_LVL_OVRD_IN Default
+	register "usb3_rx_vref_ctrl" = "0x10"
+	register "usb3_rx_vref_ctrl_en" = "0x00"
+	register "usb_3_tx_vboost_lvl" = "0x07"
+	register "usb_3_tx_vboost_lvl_en" = "0x00"
+
+	# SUPX_DIG_LVL_OVRD_IN Default
+	register "usb_3_rx_vref_ctrl_x" = "0x10"
+	register "usb_3_rx_vref_ctrl_en_x" = "0x00"
+	register "usb_3_tx_vboost_lvl_x" = "0x07"
+	register "usb_3_tx_vboost_lvl_en_x" = "0x00"
+
+	# End RV2 USB3 phy setting
+
 	# SPI Configuration
 	register "common_config.spi_config" = "{
 		.normal_speed = SPI_SPEED_33M, /* MHz */