diff options
| author | Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> | 2021-01-11 18:26:36 +0900 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-18 07:25:48 +0000 |
| commit | 4c4f9161728f42f959b4394ba42aefb64e35afe2 (patch) | |
| tree | b58d0de55d085533945ef088187a6fc69d5fdc25 /src/mainboard/google/veyron_rialto | |
| parent | 88418a74cf3c6f6cc4dc5c81cb2820a760f0c3ff (diff) | |
mb/google/dedede/var/sasuke: Disable PCIE RP8 and CLKSRC3
This change disables unused PCIE RP8 and CLKSRC3.
Without this change sasuke cannot enter into s0ix properly.
BUG=b:176862270
TEST=Built and verified entering s0ix
Change-Id: I0828813ed7924669cb0ff97be2565579762c810f
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49300
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jamie Chen <jamie.chen@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/veyron_rialto')
0 files changed, 0 insertions, 0 deletions