diff options
author | Julius Werner <jwerner@chromium.org> | 2016-09-02 11:25:56 -0700 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2016-10-04 21:20:44 +0200 |
commit | 7feb86b26b2b72d21098a90bff0843d8533a7493 (patch) | |
tree | 49373b96d35dca18a8f4f41f078569f780861934 /src/mainboard/google/veyron_mickey/sdram_inf/sdram-ddr3-nanya-2GB.inc | |
parent | f7d519c1c7ba3da1b2e459fa1a82805c70544956 (diff) |
google/gru: Ensure correct pull resistors for special-function pins
Several of the special function pins we're using in firmware have a
pre-assigned pull-up or pull-down on power-on reset. We don't want those
to interfere with any of the signaling we're trying to do on those pins,
so this patch disables them.
Also do some house-cleaning to group the bootblock code better, and
change the setup code for all SPI and I2C buses to first initialize the
controller and then mux the pins... I assume this might be a little
safer (in case the controller peripheral has some pins in a weird state
before it gets fully initialized, we don't want to mux it through too
early).
BRANCH=None
BUG=chrome-os-partner:52526
TEST=Booted Kevin.
Change-Id: I4d5bd3f7657b8113d90b65d9571583142ba10a27
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f8f7fd56e945987eb0b1124b699f676bc68d0560
Original-Change-Id: I6bcf2b9a5dc686f2b6f82bd80fc9a1a245661c47
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/382532
Reviewed-on: https://review.coreboot.org/16711
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google/veyron_mickey/sdram_inf/sdram-ddr3-nanya-2GB.inc')
0 files changed, 0 insertions, 0 deletions