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| author | Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> | 2022-09-02 16:33:32 +0800 |
|---|---|---|
| committer | Martin Roth <martin.roth@amd.corp-partner.google.com> | 2022-09-08 16:13:10 +0000 |
| commit | 7afa1bae2b8cf941ad9e8af38465030f9d1168a6 (patch) | |
| tree | fd4fdf28d30d1280e3bcec28ef5a960365fdccd0 /src/mainboard/google/veyron/reset.c | |
| parent | ed688abe51286ad071593a86126332a89bd568be (diff) | |
mb/google/brya/var/kinox: Update the DPTF parameters and fan table
Follow the Thermal_paramters_list-0902.xlsx to modify DPTF parameters
and fan table.
1. Modify CRT of TSR0 - TSR3 to 97.
2. Modify TCC offset to 6.
3. Update new fan table.
BUG=b:244657172
TEST=emerge-brask coreboot
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I751bc5442f64428c383034755cd5d74fbd0ea91e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67314
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/veyron/reset.c')
0 files changed, 0 insertions, 0 deletions