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authorSukumar Ghorai <sukumar.ghorai@intel.com>2023-07-31 18:11:04 -0700
committerMatt DeVillier <matt.devillier@amd.corp-partner.google.com>2023-08-05 16:03:37 +0000
commitc5a7d604c8e61cfc482cd7cb1f4d186d1dddef8f (patch)
tree5354e91373ffc3c8fd9ab864748d2447bbd9f09d /src/mainboard/google/sarien/Kconfig.name
parent684eca7dd2187346405180425d3537ed48db3c47 (diff)
mb/google/rex: enable d3hot for storage devices
_DSD "StorageD3Enable" property is needs to be set under the root port in the DSDT or SSDT. The ACPI _DSD method is the preferred way to opt D3hot support for storage devices. This also bypasses the low LTR from SSD that blocking S0i2.2 LTR/latency SoC requirement. Name (_DSD, Package () { ToUUID("5025030F-842F-4AB4-A561-99A5189762D0"), Package () { Package (2) {"StorageD3Enable", 1}, // 1 - Enable; 0 - Disable } } ) BUG=b:289028958 TEST=Check code compiles & boot rex, and verify the "StorageD3Enable" SSDT entry. Change-Id: I19decc2706954e73bc28fc2d9c3c4d18d2c384b7 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76835 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/sarien/Kconfig.name')
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