diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-06-04 18:55:03 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-08-31 15:12:45 +0000 |
| commit | 085649440bb1604d8492156838813938df10eb83 (patch) | |
| tree | 4fccb27d683c6372d0b72e1b03e1b966667b4373 /src/mainboard/google/poppy/variants/baseboard | |
| parent | 481661e313ddc2efb151cbdb77eeb5237eba5609 (diff) | |
mb/google/poppy: Do not let FSP-S init UART 0
FSP-S configures the GPIOs for enabled SerialIO devices. However, Poppy
boards only enable UART 0 because it's function 0 of PCI device 30, and
the PCI specification requires that function 0 of multifunction devices
be implemented if other functions are implemented as well.
Nautilus got remedied in commit 8a1f095e50e068e42d378f47c79467e7b6295b7b
(mb/google/poppy/variants/nautilus: Update camera power enable GPIOs) by
using `PchSerialIoSkipInit` for UART 0, which tells FSP to not touch the
SerialIO device. This way, it remains enabled and the GPIO settings will
not be overwritten by FSP.
However, not all variants do this, but use some UART 0 pads as GPIOs. To
prevent any issues, configure UART 0 as `PchSerialIoSkipInit` on all the
variants.
Change-Id: I7e3a61769ef9e3b348ce84c663f67d3c4c5d9485
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55236
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/poppy/variants/baseboard')
| -rw-r--r-- | src/mainboard/google/poppy/variants/baseboard/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 249183b420..ebbb12f973 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -236,7 +236,7 @@ chip soc/intel/skylake [PchSerialIoIndexI2C5] = PchSerialIoPci, [PchSerialIoIndexSpi0] = PchSerialIoDisabled, [PchSerialIoIndexSpi1] = PchSerialIoDisabled, - [PchSerialIoIndexUart0] = PchSerialIoPci, + [PchSerialIoIndexUart0] = PchSerialIoSkipInit, [PchSerialIoIndexUart1] = PchSerialIoDisabled, [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" |