diff options
| author | Julius Werner <jwerner@chromium.org> | 2013-08-15 17:34:45 -0700 |
|---|---|---|
| committer | Isaac Christensen <isaac.christensen@se-eng.com> | 2014-08-12 22:05:17 +0200 |
| commit | 79bff70ac829f45b27650671f9c33028c4b8f6c7 (patch) | |
| tree | 39181ed154fa3f8733b4623b1e210fe3db355f2c /src/mainboard/google/pit | |
| parent | e9738dbe2bb564f7be7930aa5b01e9ae3c1e2288 (diff) | |
exynos5: Refactor board-specific parts out of USB PHY code
This patch moves around some of the existing Exynos5 USB 2.0 PHY code
to make it cleaner in preparation of the 3.0 PHYs. It moves the VBUS
GPIOs (which are completely board-specific) into the mainboard code and
makes sure to only initialize PHYs on the boards that actually need
them. It also removes the USB 3.0 PLL hack that was needed on Snow from
the Pit and Kirby boards (which do not have that PLL anymore).
Change-Id: Ia35f47a765acff60481f0907f7448ec4f78e0937
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/66887
Reviewed-by: Stefan Reinauer <reinauer@google.com>
(cherry picked from commit c3b1a8b687b535f4d5ac1b3bd2a4760151698fdb)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6609
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google/pit')
| -rw-r--r-- | src/mainboard/google/pit/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/google/pit/mainboard.c | 23 |
2 files changed, 11 insertions, 14 deletions
diff --git a/src/mainboard/google/pit/devicetree.cb b/src/mainboard/google/pit/devicetree.cb index 0c687c41c3..3b6cdb9014 100644 --- a/src/mainboard/google/pit/devicetree.cb +++ b/src/mainboard/google/pit/devicetree.cb @@ -30,6 +30,4 @@ chip cpu/samsung/exynos5420 register "left_margin" = "80" register "right_margin" = "48" register "hsync" = "32" - register "usb_vbus_gpio" = "GPIO_X11" - register "usb_hsic_gpio" = "GPIO_E10" end diff --git a/src/mainboard/google/pit/mainboard.c b/src/mainboard/google/pit/mainboard.c index 9aa8d5cd30..77c54a189f 100644 --- a/src/mainboard/google/pit/mainboard.c +++ b/src/mainboard/google/pit/mainboard.c @@ -36,6 +36,7 @@ #include <cpu/samsung/exynos5420/i2c.h> #include <cpu/samsung/exynos5420/dp.h> #include <cpu/samsung/exynos5420/fimd.h> +#include <cpu/samsung/exynos5420/usb.h> #include <drivers/parade/ps8625/ps8625.h> #include <ec/google/chromeec/ec.h> #include <stdlib.h> @@ -303,7 +304,16 @@ static void backlight_en(void) gpio_direction_output(bl_en, 1); } +static enum exynos5_gpio_pin usb_drd0_vbus = GPIO_H00; +static enum exynos5_gpio_pin usb_drd1_vbus = GPIO_H01; +/* static enum exynos5_gpio_pin hsic_reset_l = GPIO_X24; */ +static void setup_usb(void) +{ + /* HSIC and USB HOST port not needed in firmware on this board */ + gpio_direction_output(usb_drd0_vbus, 1); + gpio_direction_output(usb_drd1_vbus, 1); +} static struct edp_video_info dp_video_info = { .master_mode = 0, @@ -320,16 +330,6 @@ static struct edp_video_info dp_video_info = { #define EXYNOS5420_DP1_BASE 0x145b0000 #define MAX_DP_TRIES 5 -/* - * This function disables the USB3.0 PLL to save power - */ -static void disable_usb30_pll(void) -{ - enum exynos5_gpio_pin usb3_pll_l = GPIO_Y11; - - gpio_direction_output(usb3_pll_l, 0); -} - static void setup_storage(void) { /* MMC0: Fixed, 8 bit mode, connected with GPIO. */ @@ -405,8 +405,7 @@ static void mainboard_init(device_t dev) /* Clock Gating all the unused IP's to save power */ clock_gate(); - /* Disable USB3.0 PLL to save 250mW of power */ - disable_usb30_pll(); + setup_usb(); sdmmc_vdd(); |