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| author | Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> | 2022-01-10 13:56:53 +0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-01-12 19:50:08 +0000 |
| commit | ae3f90b8f308b1b86012b52f69f34b2009db57a0 (patch) | |
| tree | 83f372fea139f934a998b16daa0dc369478599af /src/mainboard/google/oak/sdram_inf/sdram-lpddr3-MT52L512M32D2PF-4GB.inc | |
| parent | 778851366705579631f23b650edf3bc860f499e4 (diff) | |
mb/google/brya/var/taeko: Modify power sequence for SSD device
In order to avoid having the FSP fail to detect the SSD device
downstream of the RP, its PERST# must be deasserted earlier in
the boot flow, therefore move PERST# deassertion to a romstage
GPIO table.
BUG=b:213828931
TEST=Build FW and run stress exceed 1000 cycles.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I4e5eed7db16e1420ccbc22a5c30b00bedd190a2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/oak/sdram_inf/sdram-lpddr3-MT52L512M32D2PF-4GB.inc')
0 files changed, 0 insertions, 0 deletions