diff options
| author | Philipp Deppenwiese <zaolin@das-labor.org> | 2018-02-27 19:40:52 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-06-04 20:33:07 +0000 |
| commit | c07f8fbe6fd13e4245da71574b52b47e9733db84 (patch) | |
| tree | 12db8b3c40552eab81045c6165538e2d3ba36ce8 /src/mainboard/google/link | |
| parent | 961d31bdb3c97e177156ed335d6f2c726d08ab51 (diff) | |
security/tpm: Unify the coreboot TPM software stack
* Remove 2nd software stack in pc80 drivers directory.
* Create TSPI interface for common usage.
* Refactor TSS / TIS code base.
* Add vendor tss (Cr50) directory.
* Change kconfig options for TPM to TPM1.
* Add user / board configuration with:
* MAINBOARD_HAS_*_TPM # * BUS driver
* MAINBOARD_HAS_TPM1 or MAINBOARD_HAS_TPM2
* Add kconfig TPM user selection (e.g. pluggable TPMs)
* Fix existing headers and function calls.
* Fix vboot for interface usage and antirollback mode.
Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/24903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/link')
| -rw-r--r-- | src/mainboard/google/link/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/google/link/romstage.c | 2 |
2 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index 32f9fb6183..b7f0c77796 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -13,6 +13,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM1 select SERIRQ_CONTINUOUS_MODE select MAINBOARD_HAS_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index a1bbe34a4b..cc2ef22ab6 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -36,7 +36,7 @@ #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <halt.h> -#include <security/tpm/tis.h> +#include <security/tpm/tspi.h> #include <cbfs.h> #include <southbridge/intel/bd82x6x/chip.h> |