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| author | praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> | 2018-10-10 22:48:00 +0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2018-10-17 06:06:49 +0000 |
| commit | 6c96542a3e7936bcad6e2ea683f9244383a36f59 (patch) | |
| tree | f08e0c340f0a1358ed7e19c9a437e14a7e8275f0 /src/mainboard/google/link/chromeos.fmd | |
| parent | 5ac643362bb80c04329dd54281d7a9f0276d0d6b (diff) | |
drivers/intel/fsp2_0: Add new config option to support FSP CAR
CPU_MICROCODE_CBFS_LEN and CPU_MICROCODE_CBFS_LOC configs pass the CPU
microcode length and base address in CBFS to FSPT binary as init parameters.
Add new config FSP_T_XIP in Kconfig, which is selected by platform config.
If FSP_T_XIP is selected, then relocate FSPT binary while adding it in CBFS
so that it can be executed in place.
BUG= None
TEST= Build for both CFL RVP11 & RVP8 and verified for successfull CAR setup.
Change-Id: Ic46e0bb9ee13c38ff322979119c4813653c61029
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/28985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/link/chromeos.fmd')
0 files changed, 0 insertions, 0 deletions