diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2016-06-06 17:21:00 -0700 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2016-06-09 17:08:33 +0200 |
| commit | c8d45ac88e0c1170bb1b8b01a52701d96416e626 (patch) | |
| tree | 30b4a2eeaec256a4f17e69c121b1560fd07c1942 /src/mainboard/google/lars | |
| parent | 7f3156dad67ad35f02afedd85cdf4a19e3c0875e (diff) | |
skylake: Move I2C bus configuration to separate structure
Move the existing I2C voltage configuration variable into a new
structure that is equivalent, similar to how USB ports are configured.
This is to make room for additional I2C configuration options like
bus speed and whether to enable the bus in early boot which are coming
in a subsequent commit.
The affected mainboards are updated in this commit so it will build.
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Id2dea3df93e49000d60ddc66eb35d06cca6dd47e
Reviewed-on: https://review.coreboot.org/15104
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard/google/lars')
| -rw-r--r-- | src/mainboard/google/lars/devicetree.cb | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb index 5607ec83a4..fce0495a2f 100644 --- a/src/mainboard/google/lars/devicetree.cb +++ b/src/mainboard/google/lars/devicetree.cb @@ -149,7 +149,8 @@ chip soc/intel/skylake register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # SD register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port (card) register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # Type-A Port (board) - register "SerialIoI2cVoltage[4]" = "1" # I2C4 is 1.8V + + register "i2c[4].voltage" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ \ |