diff options
| author | Ravi Kumar Bokka <rbokka@codeaurora.org> | 2021-01-04 14:28:14 +0530 |
|---|---|---|
| committer | Shelley Chen <shchen@google.com> | 2021-10-07 09:03:05 +0000 |
| commit | 5afeba30a3637792d8619d52572f95b3e80e76fb (patch) | |
| tree | 2da9e7979d6a44573d86c099bda3e2789a33dd69 /src/mainboard/google/herobrine | |
| parent | 4dc9e5b3c71ba85e3aa19a98c58a86194a3fd8f5 (diff) | |
sc7280: Add SHRM firmware support
SHRM is a system hardware resource manager. It is used to manage run time
DDRSS activities. DDRSS stands for DDR subsystem.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
by trying DDR clocks which through SHRM RSI command.
Change-Id: I44484573a829eaefbd34907c6fe78d427506a762
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Diffstat (limited to 'src/mainboard/google/herobrine')
| -rw-r--r-- | src/mainboard/google/herobrine/romstage.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/herobrine/romstage.c b/src/mainboard/google/herobrine/romstage.c index 64aeaaad14..ad2d2a0c46 100644 --- a/src/mainboard/google/herobrine/romstage.c +++ b/src/mainboard/google/herobrine/romstage.c @@ -3,9 +3,11 @@ #include <arch/stages.h> #include <soc/qclib_common.h> #include "board.h" +#include <soc/shrm.h> void platform_romstage_main(void) { + shrm_fw_load_reset(); /* QCLib: DDR init & train */ qclib_load_and_run(); |