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| author | Raul E Rangel <rrangel@chromium.org> | 2021-02-19 16:01:05 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-02-25 23:42:05 +0000 |
| commit | 6e3f38392720bbedd0d493ec61c9d211a36670a8 (patch) | |
| tree | 97f02abee00ef0aed5eb29b8feabeee3d269b7e2 /src/mainboard/google/gru/devicetree.cb | |
| parent | 8e425b02451c59707b1159d9c72f53f4e5410849 (diff) | |
soc/amd/cezanne/acpi: Use IO addresses for ACPI block
This causes the linux kernel to complain:
32/64X address mismatch in FADT/Pm1aEventBlock: 0x00000400/0x00000000FED80800
32/64X address mismatch in FADT/Pm1aControlBlock: 0x00000404/0x00000000FED80804
32/64X address mismatch in FADT/PmTimerBlock: 0x00000408/0x00000000FED80808
32/64X address mismatch in FADT/Gpe0Block: 0x00000420/0x00000000FED80814
The linux kernel also verifies that the PM Timer block only uses IO
ports.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I612b6bfb67d8559127ab2ee8a2fb828493820e31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/google/gru/devicetree.cb')
0 files changed, 0 insertions, 0 deletions