diff options
| author | Kane Chen <kane.chen@intel.corp-partner.google.com> | 2023-07-12 19:11:41 +0800 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-07-18 05:31:42 +0000 |
| commit | 70c6fb42519d27bfce55a6825f52caf29fc58b71 (patch) | |
| tree | 206769035564be7c65087e5dc7068f0dba544049 /src/mainboard/google/geralt/chromeos.c | |
| parent | fa77ac93c5b63ab56135436cc34d97ab60b57470 (diff) | |
soc/intel/meteorlake: Enable PCIE_CLOCK_CONTROL_THROUGH_P2SB
On Intel Meteor Lake (MTL), PCIe CLK control register is accessed by
P2SB on IOE/SOC die.
So this patch does:
1. Enable PCIE_CLOCK_CONTROL_THROUGH_P2SB
2. Include pcie_clk.asl
3. Set the correct IOE_DIE_CLOCK_START for MTL-U/H.
BUG=b:288976547, b:289461604
TEST=Test on google/screebo and found the pcie clock is on/off properly
and sdcard PCIe port doesn't block S0ix with RTD3 cold enabled.
Change-Id: I6788ae766f36c9a0d4910fda1d6700f20ce73ea8
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76356
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/geralt/chromeos.c')
0 files changed, 0 insertions, 0 deletions