diff options
| author | Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> | 2020-05-09 16:37:30 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-26 15:02:54 +0000 |
| commit | 309ccf74dd7c25874572c6a62ffc7042dcdadc66 (patch) | |
| tree | 7b1e79798c0607ef794bb4cd24c575713a552db5 /src/mainboard/google/drallion/variants | |
| parent | 7d054bd38f5cfe36f6abd4f4422c463243bc3749 (diff) | |
cannonlake: update processor power limits configuration
Update processor power limit configuration parameters based on
common code base support for Intel Cannonlake SoC based platforms.
BRANCH=None
BUG=None
TEST=Built and tested on drallion system
Change-Id: Iac6e6f81343fcd769619e9d7ac339430966834f6
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/drallion/variants')
| -rw-r--r-- | src/mainboard/google/drallion/variants/drallion/devicetree.cb | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 9bb09abd98..e9daf0d00d 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -42,11 +42,13 @@ chip soc/intel/cannonlake register "PchUsb2PhySusPgDisable" = "1" register "speed_shift_enable" = "1" - register "psys_pmax" = "140" register "s0ix_enable" = "1" register "dptf_enable" = "1" - register "tdp_pl1_override" = "25" - register "tdp_pl2_override" = "51" + register "power_limits_config" = "{ + .tdp_pl1_override = 25, + .tdp_pl2_override = 51, + .psys_pmax = 140, + }" register "Device4Enable" = "1" register "AcousticNoiseMitigation" = "1" register "SlowSlewRateForIa" = "2" |