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authorDavid Wu <david_wu@quanta.corp-partner.google.com>2021-07-23 11:36:33 +0800
committerFelix Held <felix-coreboot@felixheld.de>2021-10-04 18:41:03 +0000
commit126162c38f47cab8569cae70373d5b512e071c14 (patch)
tree7cfa4ebcb040d250cfd3132d2ce1e3846204d867 /src/mainboard/google/deltaur
parent4a48dbe60bb39b2114f1a4c9bfc02a8d1a8e258f (diff)
mb/google/brya: Enable DDR4 SODIMM for brask
Enable SMBus to support DDR4 SODIMM for brask. Enable 'smbus' in brask device tree and add SPD addressese for the two DIMMs. Separate the Kconfig items of brya and brask. Move HAVE_SPD_IN_CBFS and CHROMEOS_DRAM_PART_NUMBER_IN_CBI to brya and add config SPD_CACHE_IN_FMAP to brask. Add a new section RW_SPD_CACHE to fmd for caching SPD data. The renamed romstage.c is used by both brya and brask and a new function variant_get_spd_info is provided to support the different SPD source types. BUG=b:194055762 BRANCH=None TEST=build pass Change-Id: I41c57a3df127356b8c7e619c4d6144dc73aeac72 Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/deltaur')
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