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authorSimon Yang <simon1.yang@intel.com>2021-12-09 19:42:24 +0800
committerNico Huber <nico.h@gmx.de>2022-01-01 14:19:53 +0000
commit355fb2fb984cc264f4452d4bbffbd3666c71906e (patch)
tree3ca8e38881caaf361ab93b9cecd8f0bd073102bb /src/mainboard/google/dedede
parente7f1f6be867dd043ca05bf24d2b7e0cfa56f80f0 (diff)
soc/intel/jasperlake: Add CdClock frequency config
Add a devicetree setting to configure the CdClock (Core Display Clock) frequency through a FSP UPD. Because the value for this UPD's default setting is non-zero and devicetree settings default to 0 if not set, adapt the devicetree values so that the value for the UPD's default setting is used when the devicetree setting is zero. Also update the comment describing the FSP UPD in the header file FspsUpd.h to match the correct CdClock definition. BUG=b:206557434 BRANCH=dedede TEST=Build fw and confirm FSP setting are set properly by log Signed-off-by: Simon Yang <simon1.yang@intel.com> Change-Id: I917c2f10b130b0cd54f60e2ba98eb971d5ec3c97 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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