diff options
| author | Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> | 2021-03-18 18:01:47 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-03-25 07:49:17 +0000 |
| commit | 4119391a8e02578b514a16735aa845366d05c774 (patch) | |
| tree | 25c416c71a856aa422eb720016eb93b6ce2f4447 /src/mainboard/google/dedede | |
| parent | e3f816c7bb77b415f53f89bf678cba2e7fbb1440 (diff) | |
mb/google/dedede/var/cret: Configure GPIO
Follow schematic to modify some GPIO pins.
GPP_C12 - NC Pin, UP_20K
GPP_C18 - NC Pin
GPP_C19 - NC Pin
GPP_C22 - NC Pin, UP_20K
GPP_D12 - NC Pin
GPP_D14 - NC Pin
GPP_D15 - NC Pin
GPP_D19 - NC Pin
GPP_D20 - NC Pin
GPP_E0 - NC Pin
GPP_E2 - NC Pin
GPP_H1 - NC Pin
GPP_H6 - NC Pin
GPP_H7 - NC Pin
GPP_G0 - NC Pin
GPP_G1 - NC Pin
GPP_G2 - NC Pin
GPP_G3 - NC Pin
GPP_G4 - NC Pin
GPP_G5 - NC Pin, UP_20K
GPP_G6 - NC Pin
GPP_G7 - NC Pin
BUG=b:183078393
BRANCH=dedede
TEST=Build the cret board.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Id966884f3e36303b636fa13ef9baecccae87604a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/mainboard/google/dedede')
| -rw-r--r-- | src/mainboard/google/dedede/variants/cret/Makefile.inc | 3 | ||||
| -rw-r--r-- | src/mainboard/google/dedede/variants/cret/gpio.c | 58 |
2 files changed, 61 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/variants/cret/Makefile.inc b/src/mainboard/google/dedede/variants/cret/Makefile.inc new file mode 100644 index 0000000000..eb2c9bc021 --- /dev/null +++ b/src/mainboard/google/dedede/variants/cret/Makefile.inc @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +ramstage-y += gpio.c diff --git a/src/mainboard/google/dedede/variants/cret/gpio.c b/src/mainboard/google/dedede/variants/cret/gpio.c new file mode 100644 index 0000000000..cb562212ae --- /dev/null +++ b/src/mainboard/google/dedede/variants/cret/gpio.c @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* C12 : AP_PEN_DET_ODL ==> NC */ + PAD_NC(GPP_C12, UP_20K), + /* C18 : AP_I2C_EMR_SDA */ + PAD_NC(GPP_C18, NONE), + /* C19 : AP_I2C_EMR_SCL */ + PAD_NC(GPP_C19, NONE), + /* C22 : UART2_RTS_N ==> NC */ + PAD_NC(GPP_C22, UP_20K), + /* D12 : WCAM_RST_L ==> NC */ + PAD_NC(GPP_D12, NONE), + /* D14 : EN_PP1200_CAMERA ==> NC */ + PAD_NC(GPP_D14, NONE), + /* D15 : UCAM_RST_L ==> NC */ + PAD_NC(GPP_D15, NONE), + /* D19 : WWAN_WLAN_COEX1 ==> NC */ + PAD_NC(GPP_D19, NONE), + /* D20 : WWAN_WLAN_COEX2 ==> NC */ + PAD_NC(GPP_D20, NONE), + /* E0 : CLK_24M_UCAM ==> NC */ + PAD_NC(GPP_E0, NONE), + /* E2 : CLK_24M_WCAM ==> NC */ + PAD_NC(GPP_E2, NONE), + /* H1 : EN_PP3300_SD_U ==> NC */ + PAD_NC(GPP_H1, NONE), + /* H6 : AP_I2C_CAM_SDA ==> NC */ + PAD_NC(GPP_H6, NONE), + /* H7 : AP_I2C_CAM_SCL ==> NC */ + PAD_NC(GPP_H7, NONE), + /* G0 : SD_CMD ==> NC */ + PAD_NC(GPP_G0, NONE), + /* G1 : SD_DATA0 ==> NC */ + PAD_NC(GPP_G1, NONE), + /* G2 : SD_DATA1 ==> NC */ + PAD_NC(GPP_G2, NONE), + /* G3 : SD_DATA2 ==> NC */ + PAD_NC(GPP_G3, NONE), + /* G4 : SD_DATA3 ==> NC */ + PAD_NC(GPP_G4, NONE), + /* G5 : SD_CD_ODL ==> NC */ + PAD_NC(GPP_G5, UP_20K), + /* G6 : SD_CLK ==> NC */ + PAD_NC(GPP_G6, NONE), + /* G7 : SD_SDIO_WP ==> NC */ + PAD_NC(GPP_G7, NONE), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} |