diff options
| author | Tao Xia <xiatao5@huaqin.corp-partner.google.com> | 2021-06-23 11:00:52 +0800 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2021-06-28 04:30:25 +0000 |
| commit | b34950e68ab14a8b049f12b6934cc71e977729a8 (patch) | |
| tree | 9af74fac5dc10b58452aa96af6e284edd87edc92 /src/mainboard/google/dedede/variants/sasukette | |
| parent | 63e98fc209a66e85e464eb36abe0da2d7eeb9ad3 (diff) | |
mb/google/dedede/var/sasukette: Update DPTF parameters
Update DPTF parameters from internal thermal team.
BUG=b:180875580
BRANCH=dedede
TEST=emerge-dedede coreboot
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: I4dbe3947779395903d7999627948d3e97d6cc985
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/mainboard/google/dedede/variants/sasukette')
| -rw-r--r-- | src/mainboard/google/dedede/variants/sasukette/overridetree.cb | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb index d1f3c56f01..a39b9d1a7d 100644 --- a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb +++ b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb @@ -75,7 +75,7 @@ chip soc/intel/jasperlake }" # Camera register "power_limits_config" = "{ - .tdp_pl1_override = 7, + .tdp_pl1_override = 6, .tdp_pl2_override = 20, }" @@ -87,8 +87,8 @@ chip soc/intel/jasperlake ## Passive Policy register "policies.passive" = "{ [0] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 52, 5000), - [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 54, 5000), - [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 54, 5000),}" + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 52, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 50, 5000),}" ## Critical Policy register "policies.critical" = "{ [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), @@ -96,7 +96,7 @@ chip soc/intel/jasperlake [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 90, SHUTDOWN), [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 90, SHUTDOWN),}" register "controls.power_limits.pl1" = "{ - .min_power = 5000, + .min_power = 3500, .max_power = 7000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 28 * MSECS_PER_SEC, |