diff options
| author | Tao Xia <xiatao5@huaqin.corp-partner.google.com> | 2021-07-22 19:54:01 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-07-28 11:40:11 +0000 |
| commit | 0f93a7b781b220b3bcddf1edabff7c8be52c9aeb (patch) | |
| tree | 8edf8adf28cbe3aaa1d25595cb6a975dad184d0f /src/mainboard/google/dedede/variants/sasukette | |
| parent | 4db34f6823f80bc2b0bd5d0b823f4b4e62f6c6ac (diff) | |
mb/google/dedede/var/sasukette: Set the xHCI LFPS period sampling off time to 0ms
LTE module L850-GL may encounter U3 wakeup race condition with the host.
Setting xHCI LFPS periodic sampling off time to 0ms so that the host would not
miss the device-initiated U3 wakeup thus avoid the race condition.
BUG=b:191426542
BRANCH=dedede
TEST=flash the image to the device. Run following command to check the bits[7:4] is 0x0:
iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: I3be7adad49f87956a6764ad91fec6e76681b393f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Chiasheng Lee <chiasheng.lee@intel.com>
Diffstat (limited to 'src/mainboard/google/dedede/variants/sasukette')
| -rw-r--r-- | src/mainboard/google/dedede/variants/sasukette/overridetree.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb index 776ba8af36..0624a0ebbb 100644 --- a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb +++ b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb @@ -81,6 +81,8 @@ chip soc/intel/jasperlake register "tcc_offset" = "10" # TCC of 95C + register "xhci_lfps_sampling_offtime_ms" = "0" + device domain 0 on device pci 04.0 on chip drivers/intel/dptf |