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authorAaron Durbin <adurbin@chromium.org>2016-07-13 13:01:13 -0500
committerAaron Durbin <adurbin@chromium.org>2016-07-15 08:30:31 +0200
commit30b0c7adf0a5d77a8e902dbbf0ee68954bf28385 (patch)
treecd13a5a401a9a4698aa3e7601f1fd91567a0269a /src/mainboard/google/cyan/acpi/dptf.asl
parent95c4344a2092bd9fd5eca74d23d0c270628f66d2 (diff)
mainboards: align on using ACPI_Sx definitions
The mainboard_smi_sleep() function takes ACPI sleep values of the form S3=3, S4=4, S5=5, etc. All the chipsets ensure that whatever hardware PM1 control register values are used the interface to the mainboard is the same. Move all the SMI handlers in the mainboard directory to not open code the literal values 3 and 5 for ACPI_S3 and ACPI_S5. There were a few notable exceptions where the code was attempting to use the hardware values and not the common translated values. The few users of SLEEP_STATE_X were updated to align with ACPI_SX as those defines are already equal. The removal of SLEEP_STATE_X defines is forthcoming in a subsequent patch. BUG=chrome-os-partner:54977 Change-Id: I76592c9107778cce5995e5af764760453f54dc50 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15664 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
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