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authorTim Wawrzynczak <twawrzynczak@chromium.org>2022-07-27 09:53:58 -0600
committerPaul Fagerburg <pfagerburg@chromium.org>2022-07-28 20:02:20 +0000
commitd6b763ca634163c9d8b9afca51f88698704c0fa9 (patch)
treec28dbb33bf5e4d628ffb9ed5ed80e45e1567ec60 /src/mainboard/google/cherry
parent05f0e3fe86d3b8572c884edb80cae5cf189f331d (diff)
soc/intel/alderlake: Add support for more CPU PCIe RP UPDs
There are 3 more CPU PCIe RP UPDs that are the current code is not setting, and some boards may want to set these, so this patch adds support to set these UPDs. The default values for any existing boards using these UPDs should not change with this patch. The UPDs are: - CpuPcieRpDetectTimeoutMs - CpuPcieRpAspm - CpuPcieRpSlotImplemented Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Id48019f984e8e53ff3ce0c3c23e02dab65112c99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66197 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/cherry')
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