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authorUsha P <usha.p@intel.com>2022-03-10 14:36:57 +0530
committerFelix Held <felix-coreboot@felixheld.de>2022-03-18 15:42:12 +0000
commitbd529e2e200a8fbfd455dd62be0494a2b727b9a5 (patch)
tree42c5bd66c306af4de5c46cb00d5a085b8c512085 /src/mainboard/google/cherry/bootblock.c
parent39e6f85ea2c1be74750a16bb2ab7a3892a7b5db1 (diff)
mb/google/nissa/var/nivviks: Add TcssAuxori for nivviks
Enable SBU orientation handling by SoC for both USBC port0 and USBC port1. Nivviks USBC port0 do not have retimer, USBC port1 has redriver, but that do not flip the data lines. Hence we need to set bits for both the USBC ports. BRANCH:None TEST=emerge-nissa coreboot chromeos-bootimage. Flash the image on nivviks board and verified USBC display is working on both the ports in normal and inverted connections. Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I219de6092ac9a9c773adbaa99f5a7d6196a2c937 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62731 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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