diff options
| author | Ren Kuo <ren.kuo@quanta.corp-partner.google.com> | 2023-01-18 16:23:54 +0800 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2023-02-05 01:03:54 +0000 |
| commit | f700ddffb1ca2c407d2c5e7f8a588bc9c81da47e (patch) | |
| tree | 34a8d3d9d2856cce48bace0dc34db01ac1b80ebc /src/mainboard/google/brya | |
| parent | f4ac5ea179af244fcb839ce20d528153f0267917 (diff) | |
mb/google/nissa/var/craask: Modify clkreq to clksrc mapping
NVMe PCIe 9-12 using clk_src1 and clk_req2 mapping to hardware design,
Due to inconsistency between PMC firmware and FSP, we need to set
clk_src to clk_req number, not same as hardware mapping in coreboot.
Then swap correct setting to clk_src=1,clk_req=2 in mFIT.
BUG=b:265720813
TEST=build firmware and veirfy suspend function on DUT.
Cq-Depend: chrome-internal:5351299
Change-Id: Ia057dfa98cb9293d9e212edb4e4ac198e94e8985
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72051
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/brya')
| -rw-r--r-- | src/mainboard/google/brya/variants/craask/gpio.c | 2 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/craask/overridetree.cb | 7 |
2 files changed, 6 insertions, 3 deletions
diff --git a/src/mainboard/google/brya/variants/craask/gpio.c b/src/mainboard/google/brya/variants/craask/gpio.c index bebc8d2138..9ccb57a5e7 100644 --- a/src/mainboard/google/brya/variants/craask/gpio.c +++ b/src/mainboard/google/brya/variants/craask/gpio.c @@ -13,7 +13,7 @@ static const struct pad_config override_gpio_table[] = { PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG), /* D6 : WWAN_EN */ PAD_CFG_GPO(GPP_D6, 1, DEEP), - /* D7 : SRCCLKREQ1# ==> SSD_CLKREQ_ODL */ + /* D7 : SRCCLKREQ2# ==> SSD_CLKREQ_ODL */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* D11 : EN_PP3300_SSD */ PAD_CFG_GPO_LOCK(GPP_D11, 1, LOCK_CONFIG), diff --git a/src/mainboard/google/brya/variants/craask/overridetree.cb b/src/mainboard/google/brya/variants/craask/overridetree.cb index 45078c92d0..5b9bf80066 100644 --- a/src/mainboard/google/brya/variants/craask/overridetree.cb +++ b/src/mainboard/google/brya/variants/craask/overridetree.cb @@ -502,9 +502,12 @@ chip soc/intel/alderlake probe SD_CARD SD_GL9750S end device ref pcie_rp9 on - # Enable NVMe SSD PCIe 9-12 using clk 2 + # Enable NVMe SSD PCIe 9-12 using clk_src1 and clk_req2 mapping to hardware + # design.Due to inconsistency between PMC firmware and FSP, we need to set + # clk_src to clk_req number, not same as hardware mapping in coreboot.Then + # swap correct setting to clk_src=1,clk_req=2 in mFIT. register "pch_pcie_rp[PCH_RP(9)]" = "{ - .clk_src = 1, + .clk_src = 2, .clk_req = 2, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" |