diff options
| author | Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> | 2021-09-03 15:08:44 +0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-09-07 21:05:49 +0000 |
| commit | c2c75ab44f05f2e393bb27665f871a639ce23a49 (patch) | |
| tree | f60952e31048a997f97e89adc16a70c17f89dade /src/mainboard/google/brya | |
| parent | eb644113057cc4f64cb42f897486fffc9c6ff27e (diff) | |
mb/google/brya/variants/gimble: add GPP_B4 and GPP_D11 to early_gpio_table
NVMe needs extra time to run boot process, enable power and deassert reset for NVMe earlier in the boot flow that gimble can successfully boot into OS with non-serial coreboot.
BUG=b:198405404
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ib76965db2a6cd0c19be4043fec73af297a619c7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57359
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/brya')
| -rw-r--r-- | src/mainboard/google/brya/variants/gimble/gpio.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/gimble/gpio.c b/src/mainboard/google/brya/variants/gimble/gpio.c index abd61b6542..8ce4f45453 100644 --- a/src/mainboard/google/brya/variants/gimble/gpio.c +++ b/src/mainboard/google/brya/variants/gimble/gpio.c @@ -114,6 +114,9 @@ static const struct pad_config override_gpio_table[] = { static const struct pad_config early_gpio_table[] = { /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ @@ -129,6 +132,9 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPP_D1, 0, DEEP), /* D2 : ISH_GP2 ==> EN_FP_PWR */ PAD_CFG_GPO(GPP_D2, 1, DEEP), + /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), + /* E0 : SATAXPCIE0 ==> NC */ PAD_NC(GPP_E0, NONE), /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ |