diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-09-21 12:56:02 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-09-26 14:21:37 +0000 |
| commit | 72bae5b9bd10a90c59d14c063c6ab58f216ddf81 (patch) | |
| tree | 994f0eae893d334dee2b984b19c51a42d28e7027 /src/mainboard/google/brya | |
| parent | 25cc4a210dbfd82e8e25b97859f09b301213b6b2 (diff) | |
mb/google/brya/var/agah: Explicitly program GPP_H13 in ramstage
In order that GPP_H13 not use the GPIO override programming from its
baseboard (brya), explicitly program GPP_H13 to a output HIGH instead
of relying on the 20K pullup from the baseboard.
BUG=b:240617195
TEST=SSD still functional
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Iddedebe2d5cfc0123932b14980d1268bcb147703
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Diffstat (limited to 'src/mainboard/google/brya')
| -rw-r--r-- | src/mainboard/google/brya/variants/agah/gpio.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/agah/gpio.c b/src/mainboard/google/brya/variants/agah/gpio.c index b55b065b8c..b496843f1d 100644 --- a/src/mainboard/google/brya/variants/agah/gpio.c +++ b/src/mainboard/google/brya/variants/agah/gpio.c @@ -131,6 +131,8 @@ static const struct pad_config override_gpio_table[] = { PAD_NC(GPP_H8, NONE), /* H9 : I2C4_SCL ==> NC */ PAD_NC(GPP_H9, NONE), + /* H13 : I2C7_SCL ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_H13, 1, DEEP), /* H19 : SRCCLKREQ4# ==> LAN_CLKREQ_ODL */ PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), /* H21 : IMGCLKOUT2 ==> NC */ |