diff options
| author | Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> | 2022-03-21 14:51:18 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-03-22 15:21:26 +0000 |
| commit | 5d3b1bbce4b3aefaee66e1d96be058397a9d7840 (patch) | |
| tree | 54328136c2924f00a9dcb4fb6d72b0601e0c8e5c /src/mainboard/google/brya/variants | |
| parent | 1f54599b9875e0de80c8636626bdfbe01646783c (diff) | |
mb/google/brya/var/kinox: Modify DDR4 to non-interleaved
Kinox is designed to 8-layer PCB. In order to reduce the length of
memory singals, the DDR4 is designed from interleaved to
non-interleaved.
BUG=b:210094309
TEST=emerge-brask coreboot
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I03c6fcccf8b1646cec1a35cc1f9cbb1cfb942c4e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Diffstat (limited to 'src/mainboard/google/brya/variants')
| -rw-r--r-- | src/mainboard/google/brya/variants/kinox/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/kinox/memory.c | 31 |
2 files changed, 32 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/kinox/Makefile.inc b/src/mainboard/google/brya/variants/kinox/Makefile.inc index 681c76498a..27174f45bf 100644 --- a/src/mainboard/google/brya/variants/kinox/Makefile.inc +++ b/src/mainboard/google/brya/variants/kinox/Makefile.inc @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c romstage-y += gpio.c +romstage-y += memory.c ramstage-y += gpio.c ramstage-y += ramstage.c diff --git a/src/mainboard/google/brya/variants/kinox/memory.c b/src/mainboard/google/brya/variants/kinox/memory.c new file mode 100644 index 0000000000..ad33e9c9c7 --- /dev/null +++ b/src/mainboard/google/brya/variants/kinox/memory.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> +#include <soc/romstage.h> + +static const struct mb_cfg ddr4_mem_config = { + .type = MEM_TYPE_DDR4, + + .rcomp = { + /* Baseboard uses only 100ohm Rcomp resistors */ + .resistor = 100, + + /* Baseboard Rcomp target values */ + .targets = {50, 20, 25, 25, 25}, + }, + + .ect = 1, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, + + .ddr_config = { + .dq_pins_interleaved = false, + }, +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &ddr4_mem_config; +} |