diff options
| author | Jamie Chen <jamie_chen@compal.corp-partner.google.com> | 2023-10-17 10:55:58 +0800 |
|---|---|---|
| committer | Matt DeVillier <matt.devillier@amd.corp-partner.google.com> | 2023-11-02 13:56:19 +0000 |
| commit | 7d3ababd71031fdb6f0cf08af41b26616efc5006 (patch) | |
| tree | 3df771829cec25e5f0d79c4e88fbb589a89bf0a4 /src/mainboard/google/brya/variants/omnigul/overridetree.cb | |
| parent | 312a277bf9b46a5624b814b1a9360bdfa517709f (diff) | |
mb/google/brya/var/omnigul: Add fingerprint SPI
Add fingerprint SPI, and power off FPMCU during romstage.
BUG=b:305860604, b:306320063
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot, measure evtest can detect and check device probed in kernel log
Change-Id: Ic7b9e29ca3cb9352fe098156924fde2719399a79
Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google/brya/variants/omnigul/overridetree.cb')
| -rw-r--r-- | src/mainboard/google/brya/variants/omnigul/overridetree.cb | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/omnigul/overridetree.cb b/src/mainboard/google/brya/variants/omnigul/overridetree.cb index b9c6d87bc3..0942299d0b 100644 --- a/src/mainboard/google/brya/variants/omnigul/overridetree.cb +++ b/src/mainboard/google/brya/variants/omnigul/overridetree.cb @@ -4,6 +4,10 @@ fw_config option STORAGE_UFS 1 option STORAGE_NVME 2 end + field FINGERPRINT 9 + option DISABLE_FP 0 + option ENABLE_FP 1 + end end chip soc/intel/alderlake @@ -318,6 +322,23 @@ chip soc/intel/alderlake device i2c 2c on end end end #I2C5 + device ref gspi1 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)" + register "wake" = "GPE0_DW2_15" + register "has_power_resource" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)" + register "enable_delay_ms" = "3" + device spi 0 hidden + probe FINGERPRINT ENABLE_FP + end + end # FPMCU + end device ref pcie_rp8 off end device ref pcie_rp9 on # Enable NVMe PCIE 9 using clk 1 |