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authorFurquan Shaikh <furquan@google.com>2021-03-05 09:10:18 -0800
committerTim Wawrzynczak <twawrzynczak@chromium.org>2021-03-06 21:14:07 +0000
commitab53c3964c7255ad4411e7a72ad3003a8f45e244 (patch)
treeb3366fd721f55a6ccbfed8cd9b990c647555f1fb /src/mainboard/google/brya/variants/brya0
parenta742681628d06b1fd200028bb7988ca80dd066e3 (diff)
mb/google/brya: Move GPE configuration to baseboard/devicetree.cb
This change moves GPE configuration from brya0/overridetree.cb to baseboard/devicetree.cb since all variants will end up using the same configuration. TEST=Verified using "abuild -p none -t google/brya -b brya0 --timeless" that coreboot.rom generated with and without this change is the same. Change-Id: Ie31bf2bf8a91da82fca77c78fb0a735a2645de55 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya/variants/brya0')
-rw-r--r--src/mainboard/google/brya/variants/brya0/overridetree.cb4
1 files changed, 0 insertions, 4 deletions
diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb
index 3ae3d80ab7..b115aeb6d7 100644
--- a/src/mainboard/google/brya/variants/brya0/overridetree.cb
+++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb
@@ -1,8 +1,4 @@
chip soc/intel/alderlake
- register "pmc_gpe0_dw0" = "GPP_A"
- register "pmc_gpe0_dw1" = "GPP_E"
- register "pmc_gpe0_dw2" = "GPP_F"
-
register "SaGv" = "SaGv_Disabled"
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port