diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-06-02 16:29:01 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-06-04 12:37:05 +0000 |
| commit | 0b7bc80eba0c7e0ece1229eacc49a6a825a1b363 (patch) | |
| tree | ecbcf8264812a6ce16c9440b0e13f2546b9e71c4 /src/mainboard/google/brya/variants/brya0 | |
| parent | c146daf8a3241026c8c8906add2b5ae37cc76427 (diff) | |
mb/google/brya/brya0: Fix irq and CS lines for FPMCU
The entries in the ACPI tables for the fingerprint module's SPI
configuration were incorrect.
1) The GPIO is routed to IOAPIC (and SCI), therefore in ACPI, it must be
described by Interrupt(), not GpioInt()
2) The chip-select signal was selected as 1, not 0 `device spi 0/1 on`
BUG=b:181635081
TEST=verified in kernel logs:
localhost # ~ dmesg|egrep 'cros-ec-dev|cros-ec-spi'
[ 4.569412] cros-ec-dev cros-ec-dev.1.auto: CrOS Fingerprint MCU detected
[ 4.575303] cros-ec-spi spi-PRP0001:00: Chrome EC device registered
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I9ef6c99f011969fc444e0c12b806529cb82bba3d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55147
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/brya/variants/brya0')
| -rw-r--r-- | src/mainboard/google/brya/variants/brya0/overridetree.cb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index 78fc472e70..6354c0d582 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -410,9 +410,9 @@ chip soc/intel/alderlake register "hid" = "ACPI_DT_NAMESPACE_HID" register "uid" = "1" register "compat_string" = ""google,cros-ec-spi"" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_F15)" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)" register "wake" = "GPE0_DW2_15" - device spi 1 on end + device spi 0 on end end # FPMCU end device ref pch_espi on |