diff options
| author | Scott Chao <scott_chao@wistron.corp-partner.google.com> | 2021-07-30 17:25:38 +0800 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2021-08-05 15:55:04 +0000 |
| commit | 6db97a31ef26ae61ce95dc8df4c4a6e74386e5d4 (patch) | |
| tree | 00cb6227b1a556d2477c2f53e3abea353e8a3fd0 /src/mainboard/google/brya/variants/baseboard | |
| parent | 2cdcc254c8d9fc9d08fd4e351872001efb894e2c (diff) | |
mb/google/brya/variants/gimble: add TcssAuxOri
Gimble don't have retimer on port0, the port need to be configured for the SOC to handle Aux orientation flipping.
Also add "typec_aux_bias_pads" lets the SoC IOM firmware control the Aux DC bias voltages.
BUG=b:195087071
BRANCH=none
TEST=check both orientation can output display on type-c monitor.
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I057048c14110bb81bf5b5fd0e3151deb031ca5d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya/variants/baseboard')
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index b8d0b5c173..aa72ae1725 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -3,6 +3,8 @@ chip soc/intel/alderlake device lapic 0 on end end + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" + # GPE configuration register "pmc_gpe0_dw0" = "GPP_A" register "pmc_gpe0_dw1" = "GPP_E" |