diff options
| author | David Wu <david_wu@quanta.corp-partner.google.com> | 2021-08-31 10:03:32 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-09-02 15:31:34 +0000 |
| commit | 14bb6f5dab90500c7d37b06f0588123bd4c58ffd (patch) | |
| tree | 32e8bbb0891f3ded9b8e2fa48b67a37065bcb1a8 /src/mainboard/google/brya/variants/baseboard | |
| parent | f496286bdce061fce5a54a8ea2befbaf2ebdb12a (diff) | |
mb/google/brya/variants/brask: Enable PCIE port 7 for Ethernet
Enable PCIE port 7 using clk 6 for RTL8125 Ethernet
BUG=b:193750191
BRANCH=None
TEST=build pass
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ic60a66dbd6ad87cf9c0de85ca7df4d854c371bf5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya/variants/baseboard')
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb index d19f627393..cc6664cd74 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb @@ -125,6 +125,14 @@ chip soc/intel/alderlake end device ref heci1 on end device ref sata on end + device ref pcie_rp7 on + # Enable PCIE 7 using clk 6 + register "pch_pcie_rp[PCH_RP(7)]" = "{ + .clk_src = 6, + .clk_req = 6, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end #PCIE7 RTL8125 Ethernet NIC device ref pcie_rp8 on # Enable SD Card PCIE 8 using clk 3 register "pch_pcie_rp[PCH_RP(8)]" = "{ |