diff options
| author | Dinesh Gehlot <digehlot@google.com> | 2024-04-05 13:08:41 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-04-10 03:29:31 +0000 |
| commit | 50b61d39dbe1e2e839f22408f27a8a87ee6d4534 (patch) | |
| tree | 35c6e2b7d67b7255889e30743873fb4d9d6061f5 /src/mainboard/google/brya/chromeos-16MiB.fmd | |
| parent | 16131f3625d9033518aa31bf740652edc7b32cc1 (diff) | |
mb/google/brya: Remove baseboard-specific FMD names
This patch renames the 16MB FMD file to remove the baseboard-specific
name 'Nissa'. This allows other supported baseboards to utilize the
16MB SPI flash. Additionally, the patch attempts to create a generic,
unified 32MB FMD file for both brya and nissa variants.
BUG=b:333314089
TEST=Build and boot Nivviks.
Change-Id: I9151a4bcbe9cc084cc19b1a3e91c0321fe4dcc37
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81676
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/brya/chromeos-16MiB.fmd')
| -rw-r--r-- | src/mainboard/google/brya/chromeos-16MiB.fmd | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/chromeos-16MiB.fmd b/src/mainboard/google/brya/chromeos-16MiB.fmd new file mode 100644 index 0000000000..037812a83f --- /dev/null +++ b/src/mainboard/google/brya/chromeos-16MiB.fmd @@ -0,0 +1,43 @@ +FLASH 16M { + SI_ALL 3712K { + SI_DESC 4K + SI_ME + } + SI_BIOS 12672K { + RW_SECTION_A 3700K { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 64 + } + RW_LEGACY(CBFS) 1M + RW_MISC 152K { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + RW_ELOG(PRESERVE) 4K + RW_SHARED 4K { + SHARED_DATA 4K + } + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 8K + } + RW_SECTION_B 3700K { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 64 + } + # Make WP_RO region align with SPI vendor + # memory protected range specification. + WP_RO 4M { + RO_VPD(PRESERVE) 16K + RO_GSCVD 8K + RO_SECTION { + FMAP 2K + RO_FRID 64 + GBB@4K 12K + COREBOOT(CBFS) + } + } + } +} |