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authorShelley Chen <shchen@google.com>2023-11-06 14:14:20 -0800
committerShelley Chen <shchen@google.com>2023-11-08 17:32:42 +0000
commit17e1c895dde6ef7b1d17902fce0949600dfd6157 (patch)
tree1cd7630dc970daf281eaf534a49bacceae45aa51 /src/mainboard/google/brox/variants
parentf931d620f6e8f6cbd9f4046cdf8498a31aecc01a (diff)
mb/google/brox: Configure early GPIOs in bootblock
Some GPIOs (like WP and GSC) need to be configured in bootblock. Making sure that they get configured earlier for this. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I8dd4853bc05b954f47d858d87ea2aed48e4b8074 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78943 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/brox/variants')
-rw-r--r--src/mainboard/google/brox/variants/baseboard/brox/gpio.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c
index 83f3a0af3b..886fdf2398 100644
--- a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c
+++ b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c
@@ -371,6 +371,14 @@ const struct pad_config *__weak variant_gpio_override_table(size_t *num)
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
+ /* GPP_E2 : THC0_SPI1_IO3 ==> GSC_PCH_INT_ODL */
+ PAD_CFG_GPI_APIC_LOCK(GPP_E2, NONE, LEVEL, INVERT, LOCK_CONFIG),
+ /* GPP_E8 : GPP_E8 ==> PCH_WP_OD */
+ PAD_CFG_GPI_LOCK(GPP_E8, NONE, LOCK_CONFIG),
+ /* GPP_H8 : [NF1: I2C4_SDA NF2: CNV_MFUART2_RXD NF6: USB_C_GPP_H8] ==> PCH_I2C_GSC_SDA */
+ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
+ /* GPP_H9 : [NF1: I2C4_SCL NF2: CNV_MFUART2_TXD] ==> PCH_I2C_GSC_SCL */
+ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
};
const struct pad_config *__weak variant_early_gpio_table(size_t *num)