Add Haswell Chromeboxes/Chromebase using variant board scheme

Combine existing board google/panther with new ChromeOS devices
mccloud, monroe, tricky, and zako, using their common reference board
(beltino) as a base.

Chromium sources used:
firmware-mccloud-5827.B 65bfee7 [haswell: No need pre-graphics delay...]
firmware-monroe-4921.B 1ac749d [Monroe: Disable KB/MS in ITE8772.]
firmware-tricky-5829.B 2db5322 [haswell: No need pre-graphics delay...]
firmware-zako-5219.B eacedef [haswell: No need pre-graphics delay...]

Existing google/panther board will be removed in a subsequent commit.

Variant setup modeled after google/reef

Change-Id: I5d7e0c2551e8b0707841032460c35615cefb2886
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17329
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

4 files changed, 326 insertions, 0 deletions

diff --git a/src/mainboard/google/beltino/variants/tricky/hda_verb.c b/src/mainboard/google/beltino/variants/tricky/hda_verb.c
new file mode 100644
index 0000000000..4d65f36a45
--- /dev/null
+++ b/src/mainboard/google/beltino/variants/tricky/hda_verb.c
@@ -0,0 +1,106 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef HDA_VERB_H
+#define HDA_VERB_H
+
+#include <stdlib.h>
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* coreboot specific header */
+	0x10ec0283,	// Codec Vendor / Device ID: Realtek ALC283
+	0x10ec0283,	// Subsystem ID
+	0x0000000e,	// Number of jacks (NID entries)
+
+	0x0017ff00,	// Function Reset
+	0x0017ff00,	// Double Function Reset
+	0x000F0000,	// Pad - get vendor id
+	0x000F0002,	// Pad - get revision id
+
+	/* NID 0x01, HDA Codec Subsystem ID Verb Table */
+	AZALIA_SUBVENDOR(0x0, 0x11790670),
+
+	/* Pin Widget Verb Table */
+
+	/* Pin Complex (NID 0x12) DMIC - Disabled */
+	AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0),
+
+	/* Pin Complex (NID 0x14) SPKR-OUT PORTD - Disabled */
+	AZALIA_PIN_CFG(0x0, 0x14, 0x401111f0),
+
+	/* Pin Complex (NID 0x17) MONO Out - Disabled */
+	AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0),
+
+	/* Pin Complex (NID 0x18) MIC1 PORTB */
+	// group 1, cap 1
+	// black, jack detect
+	// mic in, analog
+	// connector, left panel
+	AZALIA_PIN_CFG(0x0, 0x19, 0x03a71011),
+
+	/* Pin Complex (NID 0x19) MIC2 PORTF - Disabled */
+	AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0),
+
+	/* Pin Complex (NID 0x1A) LINE1 PORTC - Disabled */
+	AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0),
+
+	/* Pin Complex (NID 0x1B) LINE2 PORTE - Disabled */
+	AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0),
+
+	/* Pin Complex (NID 0x1d) PCBeep */
+	// eapd low on ex-amp, laptop, custom enable
+	// mute spkr on hpout
+	// pcbeep en able, checksum
+	// no physical, internal
+	AZALIA_PIN_CFG(0x0, 0x1d, 0x4015812d),
+
+	/* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled */
+	AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0),
+
+	/* Pin Complex (NID 0x21) HPOUT PORT-I */
+	// group1,
+	// black, jack detect
+	// HPOut, 1/8 stereo
+	// connector, left panel
+	AZALIA_PIN_CFG(0x0, 0x21, 0x0321101f),
+
+	/* Undocumented settings from Realtek (needed for beep_gen) */
+	/* Widget node 0x20 */
+	0x02050010,
+	0x02040c20,
+	0x0205001b,
+	0x0204081b,
+
+	/* Tuned jack detection */
+	0x02050043,
+	0x0204A614,
+	0x02050047,
+	0x02049470,
+};
+
+const u32 pc_beep_verbs[] = {
+	0x00170500,	/* power up everything (codec, dac, adc, mixers)  */
+	0x01470740,	/* enable speaker out */
+	0x01470c02,	/* set speaker EAPD pin */
+	0x0143b01f,	/* unmute speaker */
+	0x00c37100,	/* unmute mixer nid 0xc input 1 */
+	0x00b37410,	/* unmute mixer nid 0xb beep input and set volume */
+};
+
+
+#endif /* HDA_VERB_H */
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/google/beltino/variants/tricky/include/variant/gpio.h b/src/mainboard/google/beltino/variants/tricky/include/variant/gpio.h
new file mode 100644
index 0000000000..6980ebbe75
--- /dev/null
+++ b/src/mainboard/google/beltino/variants/tricky/include/variant/gpio.h
@@ -0,0 +1,120 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef TRICKY_GPIO_H
+#define TRICKY_GPIO_H
+
+#include <southbridge/intel/lynxpoint/lp_gpio.h>
+
+const struct pch_lp_gpio_map mainboard_gpio_map[] = {
+	LP_GPIO_UNUSED,        /* 0: UNUSED */
+	LP_GPIO_UNUSED,        /* 1: UNUSED */
+	LP_GPIO_UNUSED,        /* 2: UNUSED */
+	LP_GPIO_UNUSED,        /* 3: UNUSED */
+	LP_GPIO_NATIVE,        /* 4: NATIVE: I2C0_SDA_GPIO4 */
+	LP_GPIO_NATIVE,        /* 5: NATIVE: I2C0_SCL_GPIO5 */
+	LP_GPIO_NATIVE,        /* 6: NATIVE: I2C1_SDA_GPIO6 */
+	LP_GPIO_NATIVE,        /* 7: NATIVE: I2C1_SCL_GPIO7 */
+	LP_GPIO_ACPI_SCI,      /* 8: LAN_WAKE_L_Q */
+	LP_GPIO_OUT_HIGH,      /* 9: PP3300_WLAN_EN */
+	LP_GPIO_ACPI_SCI,      /* 10: WLAN_WAKE_L_Q */
+	LP_GPIO_UNUSED,        /* 11: SMBALERT */
+	LP_GPIO_INPUT_INVERT,  /* 12: RECOVERY_L */
+	LP_GPIO_UNUSED,        /* 13: UNUSED */
+	LP_GPIO_UNUSED,        /* 14: UNUSED */
+	LP_GPIO_UNUSED,        /* 15: UNUSED (STRAP) */
+	LP_GPIO_UNUSED,        /* 16: UNUSED */
+	LP_GPIO_OUT_HIGH,      /* 17: PP3300_VP8_EN */
+	LP_GPIO_UNUSED,        /* 18: UNUSED */
+	LP_GPIO_UNUSED,        /* 19: UNUSED */
+	LP_GPIO_NATIVE,        /* 20: NATIVE: CLK_PCIE_REQ2# */
+	LP_GPIO_NATIVE,        /* 21: NATIVE: CLK_PCIE_REQ3# */
+	LP_GPIO_NATIVE,        /* 22: NATIVE: CLK_PCIE_REQ4# */
+	LP_GPIO_UNUSED,        /* 23: UNUSED */
+	LP_GPIO_OUT_HIGH,      /* 24: WLAN_OFF_L */
+	LP_GPIO_UNUSED,        /* 25: UNUSED */
+	LP_GPIO_OUT_HIGH,      /* 26: USB_CTL_1 */
+	LP_GPIO_UNUSED,        /* 27: UNUSED */
+	LP_GPIO_OUT_LOW,       /* 28: USB_ILIM_SEL */
+	LP_GPIO_UNUSED,        /* 29: UNUSED */
+	LP_GPIO_NATIVE,        /* 30: NATIVE: PCH_SUSPWRACK_L */
+	LP_GPIO_NATIVE,        /* 31: NATIVE: PCH_ACPRESENT */
+	LP_GPIO_NATIVE,        /* 32: NATIVE: CLKRUN# */
+	LP_GPIO_NATIVE,        /* 33: NATIVE: DEVSLP0 */
+	LP_GPIO_ACPI_SMI,      /* 34: EC_SMI_L */
+	LP_GPIO_ACPI_SMI,      /* 35: PCH_NMI_DBG_L (route in NMI_EN) */
+	LP_GPIO_ACPI_SCI,      /* 36: EC_SCI_L */
+	LP_GPIO_UNUSED,        /* 37: UNUSED */
+	LP_GPIO_UNUSED,        /* 38: UNUSED */
+	LP_GPIO_UNUSED,        /* 39: UNUSED */
+	LP_GPIO_NATIVE,        /* 40: NATIVE: USB_OC0# */
+	LP_GPIO_NATIVE,        /* 41: NATIVE: USB_OC1# */
+	LP_GPIO_NATIVE,        /* 42: NATIVE: USB_OC2# */
+	LP_GPIO_NATIVE,        /* 43: NATIVE: USB_OC3# */
+	LP_GPIO_UNUSED,        /* 44: UNUSED */
+	LP_GPIO_OUT_HIGH,      /* 45: PP5000_CODEC_EN */
+	LP_GPIO_OUT_HIGH,      /* 46: BT_DISABLE_L */
+	LP_GPIO_OUT_HIGH,      /* 47: USB1_PWR_EN */
+	LP_GPIO_UNUSED,        /* 48: UNUSED */
+	LP_GPIO_UNUSED,        /* 49: UNUSED */
+	LP_GPIO_OUT_HIGH,      /* 50: VP8_DISABLE_L */
+	LP_GPIO_UNUSED,        /* 51: UNUSED */
+	LP_GPIO_UNUSED,        /* 52: UNUSED */
+	LP_GPIO_UNUSED,        /* 53: UNUSED */
+	LP_GPIO_UNUSED,        /* 54: UNUSED */
+	LP_GPIO_UNUSED,        /* 55: UNUSED */
+	LP_GPIO_OUT_HIGH,      /* 56: USB2_PWR_EN */
+	LP_GPIO_OUT_HIGH,      /* 57: USB3_PWR_EN */
+	LP_GPIO_INPUT,         /* 58: PCH_SPI_WP_D */
+	LP_GPIO_OUT_HIGH,      /* 59: PP3300_LAN_EN */
+	LP_GPIO_NATIVE,        /* 60: NATIVE: SMB0ALERT# */
+	LP_GPIO_UNUSED,        /* 61: UNUSED */
+	LP_GPIO_UNUSED,        /* 62: UNUSED */
+	LP_GPIO_NATIVE,        /* 63: NATIVE: PCH_SLP_S5_L */
+	LP_GPIO_UNUSED,        /* 64: UNUSED */
+	LP_GPIO_UNUSED,        /* 65: UNUSED */
+	LP_GPIO_UNUSED,        /* 66: UNUSED (STRAP) */
+	LP_GPIO_UNUSED,        /* 67: UNUSED */
+	LP_GPIO_UNUSED,        /* 68: UNUSED */
+	LP_GPIO_UNUSED,        /* 69: UNUSED */
+	LP_GPIO_UNUSED,        /* 70: UNUSED */
+	LP_GPIO_NATIVE,        /* 71: NATIVE: MODPHY_EN */
+	LP_GPIO_UNUSED,        /* 72: UNUSED */
+	LP_GPIO_UNUSED,        /* 73: UNUSED */
+	LP_GPIO_NATIVE,        /* 74: NATIVE: SMB_ME1_DAT */
+	LP_GPIO_NATIVE,        /* 75: NATIVE: SMB_ME1_CLK */
+	LP_GPIO_UNUSED,        /* 76: UNUSED */
+	LP_GPIO_UNUSED,        /* 77: UNUSED */
+	LP_GPIO_UNUSED,        /* 78: UNUSED */
+	LP_GPIO_UNUSED,        /* 79: UNUSED */
+	LP_GPIO_UNUSED,        /* 80: UNUSED */
+	LP_GPIO_NATIVE,        /* 81: NATIVE: SPKR */
+	LP_GPIO_NATIVE,        /* 82: NATIVE: EC_RCIN_L */
+	LP_GPIO_UNUSED,        /* 83: UNUSED */
+	LP_GPIO_UNUSED,        /* 84: UNUSED */
+	LP_GPIO_UNUSED,        /* 85: UNUSED */
+	LP_GPIO_UNUSED,        /* 86: UNUSED (STRAP) */
+	LP_GPIO_UNUSED,        /* 87: UNUSED */
+	LP_GPIO_UNUSED,        /* 88: UNUSED */
+	LP_GPIO_UNUSED,        /* 89: UNUSED */
+	LP_GPIO_UNUSED,        /* 90: UNUSED */
+	LP_GPIO_UNUSED,        /* 91: UNUSED */
+	LP_GPIO_UNUSED,        /* 92: UNUSED */
+	LP_GPIO_UNUSED,        /* 93: UNUSED */
+	LP_GPIO_UNUSED,        /* 94: UNUSED */
+	LP_GPIO_END
+};
+
+#endif
diff --git a/src/mainboard/google/beltino/variants/tricky/include/variant/thermal.h b/src/mainboard/google/beltino/variants/tricky/include/variant/thermal.h
new file mode 100644
index 0000000000..ed9e6828dd
--- /dev/null
+++ b/src/mainboard/google/beltino/variants/tricky/include/variant/thermal.h
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef THERMAL_H
+#define THERMAL_H
+
+/* Fan is OFF */
+#define FAN4_THRESHOLD_OFF	0
+#define FAN4_THRESHOLD_ON	0
+#define FAN4_PWM		0x00
+
+/* Fan is at LOW speed */
+#define FAN3_THRESHOLD_OFF	50
+#define FAN3_THRESHOLD_ON	55
+#define FAN3_PWM		0x76
+
+/* Fan is at MEDIUM speed */
+#define FAN2_THRESHOLD_OFF	59
+#define FAN2_THRESHOLD_ON	65
+#define FAN2_PWM		0x98
+
+/* Fan is at HIGH speed */
+#define FAN1_THRESHOLD_OFF	68
+#define FAN1_THRESHOLD_ON	75
+#define FAN1_PWM		0xbf
+
+/* Fan is at FULL speed */
+#define FAN0_THRESHOLD_OFF	80
+#define FAN0_THRESHOLD_ON	86
+#define FAN0_PWM		0xdc
+
+/* Temperature which OS will shutdown at */
+#define CRITICAL_TEMPERATURE	98
+
+/* Temperature which OS will throttle CPU */
+#define PASSIVE_TEMPERATURE	95
+
+/* Tj_max value for calculating PECI CPU temperature */
+#define MAX_TEMPERATURE		100
+
+#endif
diff --git a/src/mainboard/google/beltino/variants/tricky/led.c b/src/mainboard/google/beltino/variants/tricky/led.c
new file mode 100644
index 0000000000..72498a306e
--- /dev/null
+++ b/src/mainboard/google/beltino/variants/tricky/led.c
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <superio/ite/it8772f/it8772f.h>
+#include "../../onboard.h"
+
+void set_power_led(int state)
+{
+	switch (state) {
+	case LED_ON:
+	case LED_OFF:
+		it8772f_gpio_led(IT8772F_GPIO_DEV,
+			2 /* set */,
+			0xF7 /* select */,
+			state /* polarity: state dependent */,
+			0x00 /* 0=pulldown */,
+			0x04 /* output */,
+			0x04 /* 1=Simple IO function */,
+			SIO_GPIO_BLINK_GPIO22,
+			IT8772F_GPIO_BLINK_FREQUENCY_1_HZ);
+		break;
+	case LED_BLINK:
+		it8772f_gpio_led(IT8772F_GPIO_DEV,
+			2 /* set */,
+			0xF7 /* select */,
+			0x04 /* polarity */,
+			0x04 /* 1=pullup */,
+			0x04 /* output */,
+			0x00, /* 0=Alternate function */
+			SIO_GPIO_BLINK_GPIO22,
+			IT8772F_GPIO_BLINK_FREQUENCY_1_HZ);
+		break;
+	}
+}