diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-10-23 20:38:23 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-10-30 00:45:36 +0000 |
| commit | 3cc2c38d50741fffb9193851a4a3b7c636f7cd4d (patch) | |
| tree | d836bf1ee32e6132d9db9aa1f19c5779e3398ccc /src/mainboard/google/auron/variants/lulu | |
| parent | 9f6cdbaaf5d1a799e314e0baf9f4fda218abdf75 (diff) | |
soc/intel/broadwell: Separate PCH in devicetree
Flesh out the PCH configuration into a separate chip. Keep it within the
Broadwell SoC directory for now, to ease moving files around. The boards
were prepared beforehand and the devicetrees require next to no changes.
Tested on out-of-tree Acer Aspire E5-573, still boots.
Change-Id: I28d948f3e6d85e669d12b29516d867c1d1ae9e1a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46700
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/auron/variants/lulu')
| -rw-r--r-- | src/mainboard/google/auron/variants/lulu/overridetree.cb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/auron/variants/lulu/overridetree.cb b/src/mainboard/google/auron/variants/lulu/overridetree.cb index f5f3eeacdf..81110408c1 100644 --- a/src/mainboard/google/auron/variants/lulu/overridetree.cb +++ b/src/mainboard/google/auron/variants/lulu/overridetree.cb @@ -8,12 +8,12 @@ chip soc/intel/broadwell register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms device domain 0 on -# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch # DTLE DATA / EDGE values register "sata_port0_gen3_dtle" = "0x5" register "sata_port1_gen3_dtle" = "0x5" device pci 1f.2 on end # SATA Controller -# end + end end end |