mb/gigabyte/ga-h61m-s2pv: Add new mainboard

Tested with GRUB 2.02 as a payload, booting Arch Linux with
latest kernel. This code is based on the output of autoport
as well as existing ga-b75m-d3h and ga-b75m-d3v mainboards.

Working:
 - Serial port I/O
 - S3 suspend/resume (broken with SeaBIOS 1.11.1)
 - USB ports and headers
 - Gigabit Ethernet
 - Integrated graphics (libgfxinit)
 - PCIe x16 graphics
 - PCIe x1
 - SATA controller
 - Hardware Monitor
 - Fan Control (fancontrol on linux works well)
 - Native raminit (4+4GB, 4+2GB, 2+2GB, DDR3-1333)
 - Native graphics init with libgfxinit
 - flashrom, using the internal programmer. Tested with coreboot,
   as well as with the vendor firmware. Backup chip is untested.
 - NVRAM settings. Only `gfx_uma_size` and `debug_level` have been
   tested with values different from the default.

Untested:
 - VGA BIOS for integrated graphics init
 - DVI port. It can detect a "fake" display, that is, an
   EEPROM connected to the DVI port.
 - PS/2 ports
 - Audio: Only rear output (green) has been tested.
 - EHCI debug.
 - Parallel port
 - Non-Linux OSes
 - ACPI thermal zone and fan control (probably not working)

Not working:
 - SATA devices with Tianocore (payload issue)
 - PCIe to PCI bridge. It seems to be poorly supported on Linux,
   it lacks a public datasheet and vendor BIOS behaves in the
   same way: The bridge and the devices behind it appear, but
   drivers fail to find devices attached to the bridge.

Change-Id: I598a0b75093a0f1aef2ac615035d66786a8c22cb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/25912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

1 files changed, 71 insertions, 0 deletions

diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-s2pv/hda_verb.c
new file mode 100644
index 0000000000..15a2b0159c
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h61m-s2pv/hda_verb.c
@@ -0,0 +1,71 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Angel Pons <th3fanbus@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x10ec0887, /* Codec Vendor / Device ID: Realtek */
+	0x1458a002, /* Subsystem ID */
+
+	0x0000000f, /* Number of 4 dword sets */
+	/* NID 0x01: Subsystem ID.  */
+	AZALIA_SUBVENDOR(0x2, 0x1458a002),
+
+	/* NID 0x11.  */
+	AZALIA_PIN_CFG(0x2, 0x11, 0x411111f0),
+
+	/* NID 0x12.  */
+	AZALIA_PIN_CFG(0x2, 0x12, 0x411111f0),
+
+	/* NID 0x14.  */
+	AZALIA_PIN_CFG(0x2, 0x14, 0x01014410),
+
+	/* NID 0x15.  */
+	AZALIA_PIN_CFG(0x2, 0x15, 0x411111f0),
+
+	/* NID 0x16.  */
+	AZALIA_PIN_CFG(0x2, 0x16, 0x411111f0),
+
+	/* NID 0x17.  */
+	AZALIA_PIN_CFG(0x2, 0x17, 0x411111f0),
+
+	/* NID 0x18.  */
+	AZALIA_PIN_CFG(0x2, 0x18, 0x01a19c50),
+
+	/* NID 0x19.  */
+	AZALIA_PIN_CFG(0x2, 0x19, 0x02a19c60),
+
+	/* NID 0x1a.  */
+	AZALIA_PIN_CFG(0x2, 0x1a, 0x0181345f),
+
+	/* NID 0x1b.  */
+	AZALIA_PIN_CFG(0x2, 0x1b, 0x02214c20),
+
+	/* NID 0x1c.  */
+	AZALIA_PIN_CFG(0x2, 0x1c, 0x411111f0),
+
+	/* NID 0x1d.  */
+	AZALIA_PIN_CFG(0x2, 0x1d, 0x4004c601),
+
+	/* NID 0x1e.  */
+	AZALIA_PIN_CFG(0x2, 0x1e, 0x411111f0),
+
+	/* NID 0x1f.  */
+	AZALIA_PIN_CFG(0x2, 0x1f, 0x411111f0),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;