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authorFelix Singer <felixsinger@posteo.net>2024-06-23 00:25:18 +0200
committerFelix Singer <felixsinger@posteo.net>2024-06-26 11:43:56 +0000
commit6c83a71b0a803c922b02b613e927d4c49b944c32 (patch)
tree176f163e7fdeaaf1032c853e87ce5571bd921be7 /src/mainboard/facebook
parentc7c8cf2edd713fd578423bc043403ae4f91e2e29 (diff)
skl mainboards/dt: Move usb{2,3}_ports settings into XHCI device scope
Change-Id: I22ba991a9d559b0ecc7b3ceddcfd099890dd6c3a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Diffstat (limited to 'src/mainboard/facebook')
-rw-r--r--src/mainboard/facebook/monolith/devicetree.cb33
1 files changed, 17 insertions, 16 deletions
diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb
index 4bc61dd6c9..609e1811f8 100644
--- a/src/mainboard/facebook/monolith/devicetree.cb
+++ b/src/mainboard/facebook/monolith/devicetree.cb
@@ -174,21 +174,6 @@ chip soc/intel/skylake
# Disable Aspm
register "pcie_rp_aspm[8]" = "AspmDisabled"
- register "usb2_ports" = "{
- [0] = USB2_PORT_TYPE_C(OC_SKIP), /* USB-C Port 2 */
- [1] = USB2_PORT_MID(OC1), /* USB3_TYPE-A Port 1 */
- [2] = USB2_PORT_MID(OC1), /* USB3_TYPE-A Port 2 */
- [3] = USB2_PORT_TYPE_C(OC_SKIP), /* USB-C Port 1 */
- [4] = USB2_PORT_SHORT(OC_SKIP), /* M2 Port */
- [6] = USB2_PORT_SHORT(OC_SKIP), /* Audio board */
- }"
-
- register "usb3_ports" = "{
- [0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB-C Port 2 */
- [1] = USB3_PORT_DEFAULT(OC_SKIP), /* USB3_TYPE-A Port 1 */
- [2] = USB3_PORT_DEFAULT(OC_SKIP), /* USB3_TYPE-A Port 2 */
- [3] = USB3_PORT_DEFAULT(OC_SKIP), /* USB-C Port 1 */
- }"
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{
@@ -209,7 +194,23 @@ chip soc/intel/skylake
device ref igpu on end
device ref sa_thermal on end
device ref gmm on end
- device ref south_xhci on end
+ device ref south_xhci on
+ register "usb2_ports" = "{
+ [0] = USB2_PORT_TYPE_C(OC_SKIP), /* USB-C Port 2 */
+ [1] = USB2_PORT_MID(OC1), /* USB3_TYPE-A Port 1 */
+ [2] = USB2_PORT_MID(OC1), /* USB3_TYPE-A Port 2 */
+ [3] = USB2_PORT_TYPE_C(OC_SKIP), /* USB-C Port 1 */
+ [4] = USB2_PORT_SHORT(OC_SKIP), /* M2 Port */
+ [6] = USB2_PORT_SHORT(OC_SKIP), /* Audio board */
+ }"
+
+ register "usb3_ports" = "{
+ [0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB-C Port 2 */
+ [1] = USB3_PORT_DEFAULT(OC_SKIP), /* USB3_TYPE-A Port 1 */
+ [2] = USB3_PORT_DEFAULT(OC_SKIP), /* USB3_TYPE-A Port 2 */
+ [3] = USB3_PORT_DEFAULT(OC_SKIP), /* USB-C Port 1 */
+ }"
+ end
device ref south_xdci on end
device ref thermal on end
device ref heci1 on end