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authorLee Leahy <leroy.p.leahy@intel.com>2016-02-07 14:52:22 -0800
committerStefan Reinauer <stefan.reinauer@coreboot.org>2016-02-10 03:11:45 +0100
commit43cdff6b453e0563414a020c2bab69a841a8f2e8 (patch)
tree7dcd1466fe13b2be914b3af473fedf2e353ccd35 /src/mainboard/emulation
parent3968653f25d9c2147f0b74aa4467a555204a4c9b (diff)
soc/intel/quark: MTRR support
Add the SoC specific routines to access the MTRR registers. These registers exist in the host bridge and are not accessible via the rdmsr/wrmsr instructions. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Add "select DISPLAY_MTRRS" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if: * The message "FSP TempRamInit successful" is displayed Change-Id: I7c124145429ae1d1365a6222a68853edbef4ff69 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13530 Tested-by: build bot (Jenkins) Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
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