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| author | Arthur Heymans <arthur@aheymans.xyz> | 2023-05-17 18:10:47 +0200 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2023-06-04 19:22:08 +0000 |
| commit | 1efca4d570b9f9b684a6fc0d7bcdead8b0fcf1cf (patch) | |
| tree | 716894efa735c0ad6172b040882a5bd581bc2f49 /src/mainboard/emulation/spike-riscv | |
| parent | b992df98919246b70fa2f0306ba2f2056eae6271 (diff) | |
cpu/x86/smm: Drop fxsave/fxrstor logic
Since we now explicitly compile both ramstage and smihandler code
without floating point operations and associated registers we don't need
to save/restore floating point registers.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I180b9781bf5849111501ae8e9806554a7851c0da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Diffstat (limited to 'src/mainboard/emulation/spike-riscv')
0 files changed, 0 insertions, 0 deletions