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author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2024-01-18 09:59:04 +0100 |
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committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2024-02-28 17:30:57 +0000 |
commit | 8d9ce363f83b56268ec3051c1e04adb8af8813e4 (patch) | |
tree | e27152b2c2f6a2599a4c7ba4efc214d911fc0bbd /src/mainboard/emulation/qemu-riscv/uart.c | |
parent | 106d7b30b93b9d5ad4826b7dc021be69458a554f (diff) |
soc/intel/xeon_sp/util: Locate PCU by PCI device ID
Instead of manually crafting S:B:D:F numbers for each PCI device
search for the devices by PCI vendor and device ID.
This adds PCI multi-segment support without any further code
modifications, since the correct PCI segment will be stored in the
devicetree.
Change-Id: I1dcad4ba3fbc0295d74e1bf832cce95f014fd7bf
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80095
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/emulation/qemu-riscv/uart.c')
0 files changed, 0 insertions, 0 deletions