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| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2024-01-18 09:14:03 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-02-28 17:25:51 +0000 |
| commit | 106d7b30b93b9d5ad4826b7dc021be69458a554f (patch) | |
| tree | 01785042aab757a0f5fca525f1dba467982f0250 /src/mainboard/emulation/qemu-riscv/uart.c | |
| parent | 3cfcffe49c720bd5152d3a26ec744adbc4f12477 (diff) | |
soc/intel/xeon_sp: Locate PCU by PCI device ID
Instead of manually crafting S:B:D:F numbers for each PCI device
search for the devices by PCI vendor and device ID.
This adds PCI multi-segment support without any further code
modifications, since the correct PCI segment will be stored in the
devicetree.
Intel Document-ID: 735086
Intel Document-ID: 612246
Tested: On SPR 4S all PCU on all 4 sockets could be found and locked.
Change-Id: I06694715cba76b101165f1cef66d161b0f896b26
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80093
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/emulation/qemu-riscv/uart.c')
0 files changed, 0 insertions, 0 deletions