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author | Aaron Durbin <adurbin@chromium.org> | 2016-08-25 15:42:04 -0500 |
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committer | Aaron Durbin <adurbin@chromium.org> | 2016-08-30 03:15:32 +0200 |
commit | 41a3fa66a0d8a6b134ceb17b8f34520cad7643a4 (patch) | |
tree | 7e28a0a57b23ec86b10a3ee6d2d8e4699797fffd /src/mainboard/emulation/qemu-armv7/mmio.c | |
parent | a1e39248692e659d0cdf397251a8c138d290d334 (diff) |
soc/intel/apollolake: add option for SLP_S3_L assertion width
In order to provide time for the S0 rails to discharge one needs
to be able to set the SLP_S3_L assertion width. The hardware default
is 60 microcseconds which is not slow enough on most boards. Therefore
provide a devicetree option for the mainboard to set accordingly
for its needs. An unset value in devicetree results in a conservative
2 second SLP_S3_L duration.
BUG=chrome-os-partner:56581
Change-Id: I6c6df2f7a181746708ab7897249ae82109c55f50
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16326
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Diffstat (limited to 'src/mainboard/emulation/qemu-armv7/mmio.c')
0 files changed, 0 insertions, 0 deletions