diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-09-21 12:32:43 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-09-26 08:36:05 +0000 |
| commit | e52738b42889a8bf6b96fe86b87fbdd73947b367 (patch) | |
| tree | ab3ddcc914b9ab69fdb793ba42e30480d9a8824f /src/mainboard/bap/ode_e21XX | |
| parent | e1dced4561ed3b7bff98984c1d51b8e84f004b47 (diff) | |
AGESA binaryPI boards: Fix some whitespace
Change-Id: I150d4a71536137a725f43d900d483e7e35592bb3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/mainboard/bap/ode_e21XX')
| -rw-r--r-- | src/mainboard/bap/ode_e21XX/OemCustomize.c | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/src/mainboard/bap/ode_e21XX/OemCustomize.c b/src/mainboard/bap/ode_e21XX/OemCustomize.c index e97ad48db2..696a9b59eb 100644 --- a/src/mainboard/bap/ode_e21XX/OemCustomize.c +++ b/src/mainboard/bap/ode_e21XX/OemCustomize.c @@ -16,12 +16,12 @@ #include <northbridge/amd/pi/agesawrapper.h> -static const PCIe_PORT_DESCRIPTOR PortList [] = { +static const PCIe_PORT_DESCRIPTOR PortList[] = { /* Initialize Port descriptor (PCIe port, Lanes 2-3, PCI Device 2, Function 4) */ { 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 3), - PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 3), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, @@ -30,8 +30,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { /* Initialize Port descriptor (PCIe port, Lane 1, PCI Device 2, Function 3) */ { 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1), - PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, @@ -40,8 +40,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { /* Initialize Port descriptor (PCIe port, Lane 0, PCI Device 2, Function 2) */ { 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 0), - PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, @@ -50,8 +50,8 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device 2, Function 1) */ { DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7), - PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, @@ -59,18 +59,18 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { } }; -static const PCIe_DDI_DESCRIPTOR DdiList [] = { +static const PCIe_DDI_DESCRIPTOR DdiList[] = { /* eDP0 to LVDS connector */ { 0, - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1) }, /* DP1 to HDMI */ { DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2) + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux2, Hdp2) }, }; |