diff options
| author | Fabian Groffen <grobian@gentoo.org> | 2023-05-12 10:39:29 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-04-18 11:06:43 +0000 |
| commit | e8090dd1791a3c119ff88d0e5cd56de4eb6fd472 (patch) | |
| tree | 4df7dc330e0cec34b7f0f1cab2c37fe0f2d80ab2 /src/mainboard/asus | |
| parent | 0cb5e8415b2f142b3ebd910678bc007edfdb8f53 (diff) | |
mb/asus/p8z77-m: Disable WDT1
WDT1 is currently enabled but gives these errors:
[ERROR] ERROR: Resource didn't fit!!!
PNP: 002e.8 60 * size: 0x8 limit: fff io
[ERROR] PNP: 002e.8 60 io size: 0x0000000008 not assigned in devicetree
Therefore, just disable it, like it is disabled on all other variants.
Signed-off-by: Fabian Groffen <grobian@gentoo.org>
Change-Id: Ie33c219eae60f55d272b261480283a02c2d502e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75144
Reviewed-by: Keith Hui <buurin@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/asus')
| -rw-r--r-- | src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb index 5d688fd421..ee2fe9a5f4 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb @@ -47,10 +47,7 @@ chip northbridge/intel/sandybridge drq 0x22 = 0xd7 # Power down UART B and LPT end device pnp 2e.6 off end # CIR - device pnp 2e.8 on # WDT1 - drq 0xe0 = 0x7f # GP07 output - drq 0xe1 = 0x80 # GP07 high - end + device pnp 2e.8 off end # WDT1 device pnp 2e.a on # ACPI drq 0xe4 = 0x10 # Enable 3VSBSW#, needed for S3 suspend drq 0xe7 = 0x11 # HWM reset by LRESET#, 0.5s S3 delay for compatibility |