diff options
| author | Martin Roth <martin@coreboot.org> | 2021-10-01 14:37:30 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2021-10-05 18:06:52 +0000 |
| commit | 50863daef8ed75c0cb3dfd375e7622c898de5821 (patch) | |
| tree | cbb2dea518524f8c9ce5edca5d57132ca9705086 /src/mainboard/asus | |
| parent | 0949e739066c3509e05db2b9ed71cefaaa62205f (diff) | |
src/mainboard to src/security: Fix spelling errors
These issues were found and fixed by codespell, a useful tool for
finding spelling errors.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ie34003a9fdfe9f3b1b8ec0789aeca8b9435c9c79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/asus')
| -rw-r--r-- | src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb b/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb index 48376ff8bd..5efb74959f 100644 --- a/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb +++ b/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb @@ -34,7 +34,7 @@ chip northbridge/intel/x4x # Northbridge irq 0x70 = 0 irq 0xe4 = 0x10 # VSBGATE# to power dram during S3 end - device pnp 2e.b on # HWM, front pannel LED + device pnp 2e.b on # HWM, front panel LED io 0x60 = 0x290 irq 0x70 = 0 end diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c index 78ad877715..8653cec2c5 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c @@ -106,9 +106,9 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { 1, 0, 0x0080 }, /* USB3 front internal header */ { 1, 0, 0x0080 }, /* USB3 front internal header */ { 1, 1, 0x0080 }, /* USB3 ETH top connector */ - { 1, 1, 0x0080 }, /* USB3 ETH botton connector */ + { 1, 1, 0x0080 }, /* USB3 ETH bottom connector */ { 1, 2, 0x0080 }, /* USB2 PS2 top connector */ - { 1, 2, 0x0080 }, /* USB2 PS2 botton connector */ + { 1, 2, 0x0080 }, /* USB2 PS2 bottom connector */ { 1, 3, 0x0080 }, /* USB2 internal header (USB78) */ { 1, 3, 0x0080 }, /* USB2 internal header (USB78) */ { 1, 4, 0x0080 }, /* USB2 internal header (USB910) */ |