diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-09 14:29:04 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-12 18:23:07 +0000 |
| commit | c484da1a98610d783131a3a3998c0a999b97f9f5 (patch) | |
| tree | c4e25f9b4fbde15a9962b9d0c7d7117997e26ad1 /src/mainboard/asus/p5ql-em | |
| parent | fecf77770b8e68b9ef82021ca53c31db93736d93 (diff) | |
sb/intel/i82801jx: Add common code for LPC decode
Change-Id: Id706da33f06ceeec39ea50301130770226f0474e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/asus/p5ql-em')
| -rw-r--r-- | src/mainboard/asus/p5ql-em/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/asus/p5ql-em/romstage.c | 12 |
2 files changed, 3 insertions, 11 deletions
diff --git a/src/mainboard/asus/p5ql-em/devicetree.cb b/src/mainboard/asus/p5ql-em/devicetree.cb index 165340321b..fd0b1034af 100644 --- a/src/mainboard/asus/p5ql-em/devicetree.cb +++ b/src/mainboard/asus/p5ql-em/devicetree.cb @@ -49,6 +49,8 @@ chip northbridge/intel/x4x # Northbridge # Enable PCIe ports 0,1,3,4,5 as slots. register "pcie_slot_implemented" = "0x3b" + register "gen1_dec" = "0x00000295" + device pci 19.0 off end # GBE device pci 1a.0 on # USB subsystemid 0x1043 0x82d4 diff --git a/src/mainboard/asus/p5ql-em/romstage.c b/src/mainboard/asus/p5ql-em/romstage.c index 614f4874e1..142ee73e49 100644 --- a/src/mainboard/asus/p5ql-em/romstage.c +++ b/src/mainboard/asus/p5ql-em/romstage.c @@ -117,16 +117,6 @@ static void mb_gpio_init(void) RCBA8(0x31ff); } -static void ich10_enable_lpc(void) -{ - /* Configure serial IRQs.*/ - pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010); - pci_write_config16(LPC_DEV, D31F0_LPC_EN, CNF1_LPC_EN | KBC_LPC_EN - | FDD_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); - /* Hardware monitor IO range */ - pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x00000295); -} - void mainboard_romstage_entry(void) { /* This board has first dimm slot of each channel hooked up to @@ -138,7 +128,7 @@ void mainboard_romstage_entry(void) u8 s3_resume; /* Set southbridge and Super I/O GPIOs. */ - ich10_enable_lpc(); + i82801jx_lpc_setup(); mb_gpio_init(); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |