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author | Angel Pons <th3fanbus@gmail.com> | 2021-01-03 15:26:37 +0100 |
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committer | Angel Pons <th3fanbus@gmail.com> | 2021-01-06 16:50:33 +0000 |
commit | 42d033aeefe2f439c62d23dba691fd884567cac5 (patch) | |
tree | f7307d8b38c5172bb7bd4bfc28ba374650e84e8e /src/mainboard/asus/maximus_iv_gene-z/acpi | |
parent | c9a9f839cb299d26de70a6c0f1fbcb8be7aa4f0c (diff) |
nb/intel/sandybridge: Define and use `QCLK_PI` constant
To allow adjusting the phase shift of the various I/O signals, the
memory controller contains several PIs (Phase Interpolators). These
devices subdivide a QCLK (quarter of a clock cycle) in 64 `ticks`,
and the desired phase shift is specified in a register. For shifts
larger than one QCLK, there are `logic delay` registers, which allow
shifting a whole number of QCLKs in addition to the PI phase shift.
The number of PI ticks in a QCLK is often used in raminit calculations.
Define the `QCLK_PI` macro and use it in place of magic numbers. In
addition, add macros for other commonly-used values that use `QCLK_PI`
to avoid unnecessarily repeating `2 * QCLK_PI`, such as `CCC_MAX_PI`.
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change.
Change-Id: Id6ba32eb1278ef71cecb7e63bd8a95d17430ae54
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard/asus/maximus_iv_gene-z/acpi')
0 files changed, 0 insertions, 0 deletions