mainboard: Add ASRock G41C-GS

Start-point is Gigabyte GA-G41M-ES2L.

This board features a G41 northbridge and an ICH7 southbridge. This
board has slots for both DDR2 and DDR3 (cannot run concurrently
though) but only DDR2 is implemented in coreboot. The SPI flash
resides in a DIP-8 socket.

Tested and working:
* DDR2 dual channel (PC2 5300 and PC2 6400, though raminit is picky
  with assymetric dimm setups);
* 3,5" IDE;
* SATA;
* PCIe x16 (with some patches up for review);
* Uart, PS2 Keyboard;
* USB, ethernet, audio;
* Native graphic init;
* Fan control;
* Reboot, poweroff, S3 resume;
* Flashrom (vendor and coreboot).

Tested but fails:
* DDR3 (not implemented in coreboot).

Tests were run with SeaBIOS and Debian sid, using Linux 4.9.0.

Change-Id: I992ee07b742dfc59733ce0f3a9be202a530ec6cc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

1 files changed, 149 insertions, 0 deletions

diff --git a/src/mainboard/asrock/g41c-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/devicetree.cb
new file mode 100644
index 0000000000..fd7f271339
--- /dev/null
+++ b/src/mainboard/asrock/g41c-gs/devicetree.cb
@@ -0,0 +1,149 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+
+chip northbridge/intel/x4x		# Northbridge
+	device cpu_cluster 0 on		# APIC cluster
+		chip cpu/intel/socket_LGA775
+			device lapic 0 on end
+		end
+		chip cpu/intel/model_1067x		# CPU
+			device lapic 0xACAC off end
+		end
+	end
+	device domain 0 on		# PCI domain
+		subsystemid 0x1458 0x5000 inherit
+		device pci 0.0 on			# Host Bridge
+			subsystemid 0x1849 0x2e30
+		end
+		device pci 1.0 on end			# PEG
+
+		device pci 2.0 on			# Integrated graphics controller
+			subsystemid 0x1849 0x2e32
+		end
+		device pci 3.0 off end		# ME
+		device pci 3.1 off end		# ME
+		chip southbridge/intel/i82801gx	# Southbridge
+			register "pirqa_routing" = "0x0b"
+			register "pirqb_routing" = "0x0b"
+			register "pirqc_routing" = "0x0b"
+			register "pirqd_routing" = "0x0b"
+			register "pirqe_routing" = "0x80"
+			register "pirqf_routing" = "0x80"
+			register "pirqg_routing" = "0x80"
+			register "pirqh_routing" = "0x0b"
+			# GPI routing
+			#  0 No effect (default)
+			#  1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+			#  2 SCI (if corresponding GPIO_EN bit is also set)
+			register "gpi13_routing" = "2"
+
+			register "ide_enable_primary" = "0x1"
+			register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant
+			register "sata_ports_implemented" = "0x3"
+			register "gpe0_en" = "0x440"
+
+			device pci 1b.0 on		# Audio
+				subsystemid 0x1849 0x3662
+			end
+			device pci 1c.0 on end		# PCIe 1
+			device pci 1c.1 on end		# PCIe 2
+			device pci 1c.2 off end		# PCIe 3
+			device pci 1c.3 off end		# PCIe 4
+			device pci 1d.0 on		# USB
+				subsystemid 0x1849 0x27c8
+			end
+			device pci 1d.1 on		# USB
+				subsystemid 0x1849 0x27c9
+			end
+			device pci 1d.2 on		# USB
+				subsystemid 0x1849 0x27ca
+			end
+			device pci 1d.3 on		# USB
+				subsystemid 0x1849 0x27cb
+			end
+			device pci 1d.7 on		# USB
+				subsystemid 0x1849 0x27cc
+			end
+			device pci 1e.0 on end		# PCI bridge
+			device pci 1f.0 on		# ISA bridge
+				subsystemid 0x1849 0x27b8
+					chip superio/nuvoton/nct6776
+					device pnp 2e.0 off end		# Floppy
+					device pnp 2e.1 on		# Parallel port
+						# global
+						irq 0x1c = 0x80
+						irq 0x27 = 0x80
+						irq 0x2a = 0x60
+						# parallel port
+						io 0x60 = 0x378
+						irq 0x70 = 7
+						drq 0x74 = 3
+					end
+					device pnp 2e.2 on		# COM1
+						io 0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.3 off end		# COM2, IR
+					device pnp 2e.5 on		# Keyboard
+						io 0x60 = 0x60
+						io 0x62 = 0x64
+						irq 0x70 = 1
+					end
+					device pnp 2e.6 on		# CIR
+						io 0x60 = 0x230
+						irq 0x70 = 3
+					end
+					device pnp 2e.7 off end		# GPIO6-9
+					device pnp 2e.8 off end		# WDT1, GPIO0, GPIO1, GPIOA
+					device pnp 2e.9 off end		# GPIO2-5
+					device pnp 2e.a on		# ACPI
+						irq 0xe0 = 0x03
+						irq 0xe4 = 0x10 # Power dram during s3
+						irq 0xe6 = 0x4c
+						irq 0xe9 = 0x02
+						irq 0xf0 = 0x20
+					end
+					device pnp 2e.b on		# HWM, front pannel LED
+						io 0x60 = 0x290
+						io 0x62 = 0x200
+						irq 0x70 = 0
+					end
+					device pnp 2e.d on end		# VID
+					device pnp 2e.e on		# CIR WAKE-UP
+						io 0x60 = 0x240
+						irq 0x70 = 0
+					end
+					device pnp 2e.f on end		# GPIO Push-Pull or Open-drain
+					device pnp 2e.14 on end		# SVID
+					device pnp 2e.16 on end		# Deep Sleep
+					device pnp 2e.17 on end		# GPIOA
+				end
+			end
+			device pci 1f.1 on		# PATA/IDE
+				subsystemid 0x1849 0x27df
+			end
+			device pci 1f.2 on		# SATA
+				subsystemid 0x1849 0x27c0
+			end
+			device pci 1f.3 on		# SMbus
+				subsystemid 0x1849 0x27da
+			end
+			device pci 1f.4 off end
+			device pci 1f.5 off end
+			device pci 1f.6 off end
+		end
+	end
+end