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authorZheng Bao <fishbaozi@gmail.com>2021-12-06 23:09:37 +0800
committerFelix Held <felix-coreboot@felixheld.de>2022-01-25 23:57:06 +0000
commit8b54c0e04bc3488a6479180b3cb9547b4e0fc763 (patch)
treead204fae0fa75a162b8f44a5778b895564fc673c /src/mainboard/apple
parent2a404b599b3385b3246a2ee20844d2bc7a428035 (diff)
soc/amd/cezanne: FSP: Add UPD entry for eDP tuning
The FSP gets these values from the UPD and sets the internal values. The document about eDP tuning is attached in issue tracker of this ticket, at the issue tracker b/203061533#comment6. BUG=b:203061533 Cq-Depend: chrome-internal:4303901 Change-Id: I9b85faac4f2fa1fb2c14bb85b615346d4379baac Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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